Change in coreboot[master]: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
Attention is currently required from: Furquan Shaikh. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 )
Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets ......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52115/comment/be0779f7_8abd49ff PS1, Line 54: HIGH
But why? In my opinion that is not the right direction to take. […]
Until we handle the timings, which is not a part of this patch, this is the best way to go. The chips need to be powered for a while before taking them out of reset. With the current initialization steps, that's not possible.
When we do handle the timings, which can be soon, but not today, this can be addressed.
https://review.coreboot.org/c/coreboot/+/52115/comment/0da80bf7_bcb712d1 PS1, Line 169: /* EN_PP3300_WLAN */
Why is this dependent on PSP verstage?
The early gpio init is getting moved from bootblock to psp_verstage. So any timings we establish right now will be changed when that move happens. Because of the move of the PCIe training from FSP-M on Picasso to FSP-S on Cezanne, I suspect we're going to need that additional time anyway.
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Martin Roth (Code Review)