Change in coreboot[master]: northbridge/amd/pi/00730F01: enable PARALLEL_MP

[Michał Kopeć (Code Review)]

Attention is currently required from: Michał Żygowski, Paul Menzel, Angel Pons, Arthur Heymans.
Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 )

Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................

Patch Set 5:

(2 comments)

File src/northbridge/amd/pi/00730F01/northbridge.c:

https://review.coreboot.org/c/coreboot/+/59808/comment/db6d705b_8ee3a574 
PS2, Line 955: 			/*
             : 			 * APIC ID calculation is tightly coupled with AGESA v5 code.
             : 			 * This calculation MUST match the assignment calculation done
             : 			 * in LocalApicInitializationAtEarly() function.
             : 			 * And reference GetLocalApicIdForCore()
             : 			 *
             : 			 * Apply APIC enumeration rules
             : 			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
             : 			 * put the local-APICs at m..z
             : 			 *
             : 			 * This is needed because many IO-APIC devices only have 4 bits
             : 			 * for their APIC id and therefore must reside at 0..15
             : 			 */
             : 			if ((node_nums * core_max) + ioapic_count >= 0x10) {
             : 				lapicid_start = (ioapic_count - 1) / core_max;
             : 				lapicid_start = (lapicid_start + 1) * core_max;
             : 				printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start);
             : 			}
             : 			u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
             : 			printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
             : 					i, j, apic_id);
             : 
             : 			struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
             : 			if (cpu)
             : 				amd_cpu_topology(cpu, i, j);
> Removed

Done

File src/northbridge/amd/pi/00730F01/northbridge.c:

https://review.coreboot.org/c/coreboot/+/59808/comment/ac9856b8_55b2ac3f 
PS4, Line 900: /* The flash is now no longer cacheable. Reset to WP for performance. */
             : 	mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
             : 			    MTRR_TYPE_WRPROT);
> If I do it in `pre_mp_init`, Linux complains about inconsistent MTRRs. […]

Done