Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27006
Change subject: soc/intel/cannonlake: Use pci_devfn_t instead of device_t ......................................................................
soc/intel/cannonlake: Use pci_devfn_t instead of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Ie59263543a2ccbcf0b13a597f8ae82ea8334fea6 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/cannonlake/smmrelocate.c 4 files changed, 11 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/27006/1
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 8e4f7fd..dc70a4f 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -52,7 +52,7 @@
static void enable_p2sbbar(void) { - device_t dev = PCH_DEV_P2SB; + pci_devfn_t dev = PCH_DEV_P2SB;
/* Enable PCR Base address in PCH */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index c81e534..a2cd864 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -69,12 +69,12 @@ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, };
-static uint8_t get_dev_revision(device_t dev) +static uint8_t get_dev_revision(pci_devfn_t dev) { return pci_read_config8(dev, PCI_REVISION_ID); }
-static uint16_t get_dev_id(device_t dev) +static uint16_t get_dev_id(pci_devfn_t dev) { return pci_read_config16(dev, PCI_DEVICE_ID); } @@ -140,7 +140,7 @@ static void report_mch_info(void) { int i; - device_t dev = SA_DEV_ROOT; + pci_devfn_t dev = SA_DEV_ROOT; uint16_t mchid = get_dev_id(dev); uint8_t mch_revision = get_dev_revision(dev); const char *mch_type = "Unknown"; @@ -159,7 +159,7 @@ static void report_pch_info(void) { int i; - device_t dev = PCH_DEV_LPC; + pci_devfn_t dev = PCH_DEV_LPC; uint16_t lpcid = get_dev_id(dev); const char *pch_type = "Unknown";
@@ -176,7 +176,7 @@ static void report_igd_info(void) { int i; - device_t dev = SA_DEV_IGD; + pci_devfn_t dev = SA_DEV_IGD; uint16_t igdid = get_dev_id(dev); const char *igd_type = "Unknown";
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index ba010aa..0ecc66d 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -35,7 +35,8 @@ return &em64t101_smm_ops; }
-static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) +static void pch_configure_endpoints(pci_devfn_t dev, int epmask_id, + uint32_t mask) { uint32_t reg32;
@@ -43,7 +44,7 @@ pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); }
-static void disable_sideband_access(device_t dev) +static void disable_sideband_access(pci_devfn_t dev) { u8 reg8; uint32_t mask; @@ -60,7 +61,7 @@
static void pch_disable_heci(void) { - device_t dev = PCH_DEV_P2SB; + pci_devfn_t dev = PCH_DEV_P2SB; struct pcr_sbi_msg msg = { .pid = PID_CSME0, .offset = 0, diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 83330e6..3c60ef2 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -255,7 +255,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT;
printk(BIOS_DEBUG, "Setting up SMI for CPU\n");