Change in ...coreboot[master]: cpu/intel/microcode_asm.S: Fix reading cpuid(1) and checking PF

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30680

Change subject: cpu/intel/microcode_asm.S: Fix reading cpuid(1) and checking PF
......................................................................

cpu/intel/microcode_asm.S: Fix reading cpuid(1) and checking PF

The value of %ebx was clobber later on by a cpuid call.

A bitwise and needs to be used to check processor flags.

Change-Id: I29f1fddfe3cc2cbfc7c843b6aff7425f32e12317
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/microcode/microcode_asm.S
1 file changed, 5 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30680/1

diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S
index ef85760..e158e61 100644
--- a/src/cpu/intel/microcode/microcode_asm.S
+++ b/src/cpu/intel/microcode/microcode_asm.S
@@ -83,11 +83,6 @@
     * Current installed microcode revision -> %edx
     */

-	/* Processor family+model signature=cpuid_eax(1) */
-	movl	$1, %eax
-	cpuid
-	movl	%eax, %ebx
-
    /* Processor flags
     * rdmsr 0x17
     * pf = 1 << ((msr.hi >> 18) & 7) */
@@ -108,6 +103,10 @@
    wrmsr
    movl	$0x1, %eax
    cpuid
+
+	/* Processor family+model signature=cpuid_eax(1) */
+	movl	%eax, %ebx
+
    movl	$IA32_BIOS_SIGN_ID, %ecx
    rdmsr

@@ -121,7 +120,7 @@
    jne	next_entry

/* Processor flags */
-	cmpl	PROCESSOR_FLAG(%esi), %ebp
+	test	PROCESSOR_FLAG(%esi), %ebp
    jne	next_entry

/* Check if revision is higher than current */