[XS] Change in coreboot[main]: soc/intel: separate slp-s0 residency counter frequency in LPIT table

[Paul Menzel (Code Review)]

Attention is currently required from: Sukumar Ghorai.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78177?usp=email )

Change subject: soc/intel: separate slp-s0 residency counter frequency in LPIT table
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Patch Set 10:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/78177/comment/34114c2f_dc9c5c81 :
PS10, Line 25: 
It would have been nice, if you had stated, that the code didn’t change, as the new macro is also defined as 0.

File src/include/acpi/acpi.h:

https://review.coreboot.org/c/coreboot/+/78177/comment/0d6435a1_9a380213 :
PS10, Line 456: #define ACPI_LPIT_CTR_FREQ_TSC	0
              : #define ACPI_LPIT_SLP_S0_FREQ	0
Only at the top of the file, the values are aligned with tabs. After that spaces are used. Maybe keep that?