[S] Change in coreboot[main]: cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_*

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86683?usp=email )

(

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_*
......................................................................

cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_*

AMD64 spec refers to the field as MT (Message Type), but the IA64 spec
refers to it as DM (Delivery Mode). The problem is that there is another
field abbreviated as DM (Destination Mode) right next to it. So for
better readability, just stick to the AMD64 terminology.

Signed-off-by: Maximilian Brune 
Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86683
Tested-by: build bot (Jenkins) 
Reviewed-by: Andy Ebrahiem 
Reviewed-by: Jérémy Compostella 
Reviewed-by: Shuo Liu 
---
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/x86/lapic/lapic_cpu_stop.c
M src/cpu/x86/mp_init.c
M src/include/cpu/x86/lapic_def.h
4 files changed, 16 insertions(+), 15 deletions(-)

Approvals:
  Andy Ebrahiem: Looks good to me, but someone else must approve
  Jérémy Compostella: Looks good to me, approved
  Shuo Liu: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified

diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 1843954..1ce28a4 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -111,7 +111,7 @@

/* Send INIT IPI to all excluding ourself. */
    movl	LAPIC(ICR), %edi
-	movl	$(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
+	movl	$(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_MT_INIT), %eax
 1:	movl	%eax, (%edi)
    movl	$0x30, %ecx
 2:	pause
@@ -160,7 +160,7 @@

/* Send Start IPI to all excluding ourself. */
    movl	LAPIC(ICR), %edi
-	movl	$(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP), %eax
+	movl	$(LAPIC_DEST_ALLBUT | LAPIC_MT_STARTUP), %eax
    orl	$ap_sipi_vector_in_rom, %eax
 1:	movl	%eax, (%edi)
    movl	$0x30, %ecx
diff --git a/src/cpu/x86/lapic/lapic_cpu_stop.c b/src/cpu/x86/lapic/lapic_cpu_stop.c
index 6eacba6..1709b95 100644
--- a/src/cpu/x86/lapic/lapic_cpu_stop.c
+++ b/src/cpu/x86/lapic/lapic_cpu_stop.c
@@ -56,7 +56,7 @@
    printk(BIOS_DEBUG, "CPU %ld going down...\n", id);

/* send an LAPIC INIT to myself */
-	lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
+	lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_MT_INIT);
    wait_for_ipi_completion_without_printk(timeout_100ms);

mdelay(10);
@@ -64,7 +64,7 @@
    dprintk(BIOS_SPEW, "Deasserting INIT.\n");

/* Deassert the LAPIC INIT */
-	lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
+	lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_MT_INIT);
    wait_for_ipi_completion_without_printk(timeout_100ms);

halt();
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 47b3a9e..574f28e 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -434,7 +434,7 @@
    	printk(BIOS_DEBUG, "done.\n");
    }

-	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector);
+	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_STARTUP | sipi_vector);
    printk(BIOS_DEBUG, "Waiting for SIPI to complete...\n");
    if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */) != CB_SUCCESS) {
    	printk(BIOS_ERR, "timed out.\n");
@@ -474,7 +474,7 @@
    }

/* Send INIT IPI to all but self. */
-	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_INIT);
+	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_INIT);

if (!CONFIG(X86_INIT_NEED_1_SIPI)) {
    	printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n");
@@ -658,7 +658,7 @@
    	printk(BIOS_DEBUG, "done.\n");
    }

-	lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_DM_SMI);
+	lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_MT_SMI);

if (lapic_busy()) {
    	if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */) != CB_SUCCESS) {
diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h
index e118b6b..cb5482c 100644
--- a/src/include/cpu/x86/lapic_def.h
+++ b/src/include/cpu/x86/lapic_def.h
@@ -42,14 +42,15 @@
 #define		LAPIC_INT_ASSERT		0x04000
 #define		LAPIC_ICR_BUSY		0x01000
 #define		LAPIC_DEST_LOGICAL	0x00800
-#define		LAPIC_DM_FIXED		0x00000
-#define		LAPIC_DM_LOWEST		0x00100
-#define		LAPIC_DM_SMI		0x00200
-#define		LAPIC_DM_REMRD		0x00300
-#define		LAPIC_DM_NMI		0x00400
-#define		LAPIC_DM_INIT		0x00500
-#define		LAPIC_DM_STARTUP		0x00600
-#define		LAPIC_DM_EXTINT		0x00700
+// AMD64 refers to it as MT (Message Type), but IA-64 refers to it as DM (Delivery Mode)
+#define		LAPIC_MT_FIXED		0x00000
+#define		LAPIC_MT_LOWEST		0x00100
+#define		LAPIC_MT_SMI		0x00200
+#define		LAPIC_MT_REMRD		0x00300
+#define		LAPIC_MT_NMI		0x00400
+#define		LAPIC_MT_INIT		0x00500
+#define		LAPIC_MT_STARTUP		0x00600
+#define		LAPIC_MT_EXTINT		0x00700
 #define		LAPIC_VECTOR_MASK	0x000FF
 #define LAPIC_ICR2	0x310
 #define		GET_LAPIC_DEST_FIELD(x)	(((x)>>24)&0xFF)