Change in coreboot[master]: mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants
Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37912 )
Change subject: mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants ......................................................................
mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants
Unlike other x7x boards, the ga-b75m-d3h lacks definitions to wire SuperSpeed-capable ports to XHCI in its device tree, causing these ports being wired to the second EHCI, and only working as USB 2.0 ports.
This change will add them.
Tested on my ga-b75-d3v board.
Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37912/1
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 57b4960..7b47067 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -38,6 +38,9 @@ register "sata_port_map" = "0x3f" register "sata_interface_speed_support" = "0x3"
+ register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "pcie_port_coalesce" = "0" register "docking_supported" = "0" register "c2_latency" = "0x0065"
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37912 )
Change subject: mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants ......................................................................
Patch Set 1: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/37912/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37912/1//COMMIT_MSG@9 PS1, Line 9: x7x Panther Point
https://review.coreboot.org/c/coreboot/+/37912/1//COMMIT_MSG@10 PS1, Line 10: device tree devicetree
https://review.coreboot.org/c/coreboot/+/37912/1//COMMIT_MSG@14 PS1, Line 14: This change will add them. This could be rephrased and appended to the previous paragraph:
Add the missing registers to fix that.
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37912
to look at the new patch set (#2).
Change subject: mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants ......................................................................
mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants
Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions to wire SuperSpeed-capable ports to XHCI in its devicetree, causing these ports being wired to the second EHCI, and only working as USB 2.0 ports. The missing register definitions are added to fix that.
Tested on my ga-b75-d3v board.
Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37912/2
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37912 )
Change subject: mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37912/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37912/1//COMMIT_MSG@9 PS1, Line 9: x7x
Panther Point
Done
https://review.coreboot.org/c/coreboot/+/37912/1//COMMIT_MSG@10 PS1, Line 10: device tree
devicetree
Done
https://review.coreboot.org/c/coreboot/+/37912/1//COMMIT_MSG@14 PS1, Line 14: This change will add them.
This could be rephrased and appended to the previous paragraph: […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37912 )
Change subject: mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37912 )
Change subject: mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants ......................................................................
mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants
Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions to wire SuperSpeed-capable ports to XHCI in its devicetree, causing these ports being wired to the second EHCI, and only working as USB 2.0 ports. The missing register definitions are added to fix that.
Tested on my ga-b75-d3v board.
Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513 Signed-off-by: Bill XIE persmule@hardenedlinux.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/37912 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 57b4960..7b47067 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -38,6 +38,9 @@ register "sata_port_map" = "0x3f" register "sata_interface_speed_support" = "0x3"
+ register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "pcie_port_coalesce" = "0" register "docking_supported" = "0" register "c2_latency" = "0x0065"
-
Angel Pons (Code Review) -
Bill XIE (Code Review)
-
Patrick Georgi (Code Review)