New patch to review for coreboot: fcddc24 exynos5250: Add functions for configuring L2 cache

[David Hendricks]

David Hendricks ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2949

-gerrit

commit fcddc243428064380ca53ef816f20f3c8e9c45ba
Author: David Hendricks 
Date:   Thu Mar 28 19:04:58 2013 -0700

exynos5250: Add functions for configuring L2 cache

This adds functions to configure L2 cache.

Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224
    Signed-off-by: David Hendricks 
---
 src/cpu/samsung/exynos5250/cpu.c | 16 ++++++++++++++++
 src/cpu/samsung/exynos5250/cpu.h |  2 ++
 2 files changed, 18 insertions(+)

diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index b6eae46..7b58ae1 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -1,5 +1,7 @@
 #include <console/console.h>
 #include <device/device.h>
+#include <arch/cache.h>
+#include <cpu/samsung/exynos5250/cpu.h>

#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
 #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
@@ -33,3 +35,17 @@ struct chip_operations cpu_samsung_exynos5250_ops = {
    CHIP_NAME("CPU Samsung Exynos 5250")
    .enable_dev = enable_dev,
 };
+
+void exynos5_config_l2_cache(void)
+{
+	uint32_t val = read_l2ctlr();
+
+	/*
+	 * Bit    9 - L2 tag RAM setup (1 cycle)
+	 * Bits 8:6 - L2 tag RAM latency (3 cycles)
+	 * Bit    5 - L2 data RAM setup (1 cycle)
+	 * Bits 2:0 - L2 data RAM latency (3 cycles)
+	 */
+	val |= (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2);
+	write_l2ctlr(val);
+}
diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h
index 772e591..83b3292 100644
--- a/src/cpu/samsung/exynos5250/cpu.h
+++ b/src/cpu/samsung/exynos5250/cpu.h
@@ -118,4 +118,6 @@
 /* helper function to map mmio address to peripheral id */
 enum periph_id exynos5_get_periph_id(unsigned base_addr);

+void exynos5_config_l2_cache(void);
+
 #endif	/* _EXYNOS5250_CPU_H */