Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
soc/intel/tigerlake: Update Kconfig related to JSL
Update Kconfig: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE 2. Update the right value of MAX_ROOT_PORTS and MAX_PCIE_CLOCKS for SOC_INTEL_JASPERLAKE
Change-Id: I4aa52c80bfd6134164a0925ea548579b3cc54a55 Signed-off-by: Usha P usha.p@intel.com --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38678/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0..070fc89 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -12,7 +12,7 @@ config SOC_INTEL_JASPERLAKE bool select SOC_INTEL_TIGERLAKE_BASE - select INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM help Intel Jasperlake support
@@ -113,13 +113,13 @@
config MAX_ROOT_PORTS int - default 16 if SOC_INTEL_JASPERLAKE + default 8 if SOC_INTEL_JASPERLAKE default 12 if SOC_INTEL_TIGERLAKE
config MAX_PCIE_CLOCKS int default 7 if SOC_INTEL_TIGERLAKE - default 16 if SOC_INTEL_JASPERLAKE + default 5 if SOC_INTEL_JASPERLAKE
config SMM_TSEG_SIZE hex
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38678/2//COMMIT_MSG@10 PS2, Line 10: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE This made me curious, is there no Cache-QoS support like in APL?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38678/2//COMMIT_MSG@10 PS2, Line 10: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE
This made me curious, is there no Cache-QoS support like in APL?
no Nico, we are seeing some issue with NEM enhanced mode like other SoC we support. hence we have fall back to NEM only mode till that issue got resolved.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38678/2//COMMIT_MSG@10 PS2, Line 10: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE
no Nico, we are seeing some issue with NEM enhanced mode like other SoC we support. […]
As I understand it, we support another mode beside NEM (enhanced) for APL. In common/block/cpu/Kconfig we have: * config INTEL_CAR_NEM * config INTEL_CAR_CQOS * config INTEL_CAR_NEM_ENHANCED.
It's the CQOS option that I was referring to.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38678/2//COMMIT_MSG@10 PS2, Line 10: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE
As I understand it, we support another mode beside NEM (enhanced) for APL. […]
got it. CQOS and NEM enhance both are derived from CAT (cache allocation technology) and on APL/GPL, CQOS was applicable. We are expecting NEM enhance should work on latest CPU, will get back on this
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/2/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/38678/2/src/soc/intel/tigerlake/Kco... PS2, Line 122: 5 Is it 5 or 6? I see in EDS that there are 6 PCIE_CLKREQ[0..5]_N signals.
Hello Patrick Rudolph, Karthikeyan Ramasubramanian, Subrata Banik, Sridhar Siricilla, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38678
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
soc/intel/tigerlake: Update Kconfig related to JSL
Update Kconfig: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE 2. Update the right value of MAX_ROOT_PORTS and MAX_PCIE_CLOCKS for SOC_INTEL_JASPERLAKE
Change-Id: I4aa52c80bfd6134164a0925ea548579b3cc54a55 Signed-off-by: Usha P usha.p@intel.com --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38678/3
Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/2/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/38678/2/src/soc/intel/tigerlake/Kco... PS2, Line 122: 5
Is it 5 or 6? I see in EDS that there are 6 PCIE_CLKREQ[0..5]_N signals.
Yes, it has to be 6. Updated same, Thanks.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 3: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/38678/3/src/soc/intel/tigerlake/Kco... PS3, Line 15: INTEL_CAR_NEM Why? Did you observe any issue? Is there a partner bug raised for that?
Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/38678/3/src/soc/intel/tigerlake/Kco... PS3, Line 15: INTEL_CAR_NEM
Why? Did you observe any issue? Is there a partner bug raised for that?
Yes. Observed a hang in bootblock while using INTEL_CAR_NEM_ENHANCED mode.
I have raised a crosbug to track on the same. Will be adding the debug data on this crosbug. https://partnerissuetracker.corp.google.com/issues/149273819
Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/38678/3/src/soc/intel/tigerlake/Kco... PS3, Line 15: INTEL_CAR_NEM
Yes. Observed a hang in bootblock while using INTEL_CAR_NEM_ENHANCED mode. […]
Hi Furquan,we have updated the debug data on the crosbug. Can we mark this comment as resolved ?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/38678/3/src/soc/intel/tigerlake/Kco... PS3, Line 15: INTEL_CAR_NEM
Hi Furquan,we have updated the debug data on the crosbug. […]
Done. Thanks!
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
soc/intel/tigerlake: Update Kconfig related to JSL
Update Kconfig: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE 2. Update the right value of MAX_ROOT_PORTS and MAX_PCIE_CLOCKS for SOC_INTEL_JASPERLAKE
Change-Id: I4aa52c80bfd6134164a0925ea548579b3cc54a55 Signed-off-by: Usha P usha.p@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38678 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Aamir Bohra aamir.bohra@intel.com Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0..1b90d4b 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -12,7 +12,7 @@ config SOC_INTEL_JASPERLAKE bool select SOC_INTEL_TIGERLAKE_BASE - select INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM help Intel Jasperlake support
@@ -113,13 +113,13 @@
config MAX_ROOT_PORTS int - default 16 if SOC_INTEL_JASPERLAKE + default 8 if SOC_INTEL_JASPERLAKE default 12 if SOC_INTEL_TIGERLAKE
config MAX_PCIE_CLOCKS int default 7 if SOC_INTEL_TIGERLAKE - default 16 if SOC_INTEL_JASPERLAKE + default 6 if SOC_INTEL_JASPERLAKE
config SMM_TSEG_SIZE hex
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/4/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/38678/4/src/soc/intel/tigerlake/Kco... PS4, Line 122: default 6 if SOC_INTEL_JASPERLAKE Jasperlake RVP uses higher indices which breaks the build. What gives?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/4/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/38678/4/src/soc/intel/tigerlake/Kco... PS4, Line 122: default 6 if SOC_INTEL_JASPERLAKE
Jasperlake RVP uses higher indices which breaks the build. […]
@aamir, can you please check this on high priority as Patrick is telling, it breaks build
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38678 )
Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38678/4/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/38678/4/src/soc/intel/tigerlake/Kco... PS4, Line 122: default 6 if SOC_INTEL_JASPERLAKE
@aamir, can you please check this on high priority as Patrick is telling, it breaks build
Hi Patrick Subrata, sorry for the inconvenience. Below CL should fix it. https://review.coreboot.org/c/coreboot/+/38679
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Aamir Bohra (Code Review) -
Furquan Shaikh (Code Review)
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Karthik Ramasubramanian (Code Review)
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Nico Huber (Code Review)
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Patrick Georgi (Code Review)
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Subrata Banik (Code Review)
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Usha P (Code Review)