[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Enable ASPM for PCIe4 SSD of CPU

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84279?usp=email )

Change subject: mb/google/brox/var/jubilant: Enable ASPM for PCIe4 SSD of CPU
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mb/google/brox/var/jubilant: Enable ASPM for PCIe4 SSD of CPU

Enable ASPM of CPU PCIe4 for SSD to improve power consumption.

BUG=b:364441213
BRANCH=None
TEST="sh -c 'lspci -vvnn || lspci -nn'"
      01:00.0 Non-Volatile memory controller
      LnkCtl:	ASPM L1 Enabled

Change-Id: I4380bb8748f2847b1824e20edb19578c7aedfe4f
Signed-off-by: Ren Kuo 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84279
Tested-by: build bot (Jenkins) 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Subrata Banik 
---
M src/mainboard/google/brox/variants/jubilant/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb
index 52a3236..2e7234d 100644
--- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb
+++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb
@@ -275,6 +275,7 @@
    			.clk_req = 3,
    			.clk_src = 3,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1,
    		}"
    		probe STORAGE STORAGE_NVME
    		probe unprovisioned