[L] Change in coreboot[main]: soc/intel/xeon_sp: Share DDR codes acorss Xeon-SP platforms

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.

Shuo Liu has uploaded a new patch set (#10) to the change originally created by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/81219?usp=email )

Change subject: soc/intel/xeon_sp: Share DDR codes acorss Xeon-SP platforms
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soc/intel/xeon_sp: Share DDR codes acorss Xeon-SP platforms

DDR support codes across generations are similar. Share the codes
to improve code reuse.

TEST=intel/archercity CRB

Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf
Signed-off-by: Jincheng Li 
---
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/cpx/Makefile.mk
D src/soc/intel/xeon_sp/cpx/ddr.c
D src/soc/intel/xeon_sp/cpx/include/soc/ddr.h
R src/soc/intel/xeon_sp/ddr.c
A src/soc/intel/xeon_sp/include/soc/ddr.h
M src/soc/intel/xeon_sp/spr/Makefile.mk
D src/soc/intel/xeon_sp/spr/include/soc/ddr.h
M src/soc/intel/xeon_sp/spr/romstage.c
9 files changed, 77 insertions(+), 207 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81219/10