[S] Change in coreboot[main]: nb/amd/pi/00730F01: add CPU and domain ops in devicetree

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79085?usp=email )

(

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: nb/amd/pi/00730F01: add CPU and domain ops in devicetree
......................................................................

nb/amd/pi/00730F01: add CPU and domain ops in devicetree

Add the CPU and PCI domain operation bindings statically in the chipset
devicetree instead of adding them during runtime.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held 
Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier 
Reviewed-by: Nico Huber 
---
M src/northbridge/amd/pi/00730F01/chipset.cb
M src/northbridge/amd/pi/00730F01/northbridge.c
2 files changed, 6 insertions(+), 14 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve
  Matt DeVillier: Looks good to me, approved

diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb
index 57f89c4..bc79426 100644
--- a/src/northbridge/amd/pi/00730F01/chipset.cb
+++ b/src/northbridge/amd/pi/00730F01/chipset.cb
@@ -1,9 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0-only

chip northbridge/amd/pi/00730F01
-	device cpu_cluster 0 on end
+	device cpu_cluster 0 on
+		ops amd_fam16_mod30_cpu_bus_ops
+	end

device domain 0 on
+		ops amd_fam16_mod30_pci_domain_ops
    	device pci 0.0 alias gnb			on  end
    	device pci 0.2 alias iommu			off end
    	device pci 1.0 alias gfx			off end
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index e8f7abd..3ac94e5 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -831,7 +831,7 @@
    return NULL;
 }

-static struct device_operations pci_domain_ops = {
+struct device_operations amd_fam16_mod30_pci_domain_ops = {
    .read_resources	  = domain_read_resources,
    .set_resources	  = pci_domain_set_resources,
    .scan_bus	  = pci_host_bridge_scan_bus,
@@ -863,26 +863,15 @@
    }
 }

-static struct device_operations cpu_bus_ops = {
+struct device_operations amd_fam16_mod30_cpu_bus_ops = {
    .read_resources	= noop_read_resources,
    .set_resources	= noop_set_resources,
    .init		= mp_cpu_bus_init,
    .acpi_fill_ssdt	= generate_cpu_entries,
 };

-static void root_complex_enable_dev(struct device *dev)
-{
-	/* Set the operations if it is a special bus type */
-	if (dev->path.type == DEVICE_PATH_DOMAIN) {
-		dev->ops = &pci_domain_ops;
-	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
-		dev->ops = &cpu_bus_ops;
-	}
-}
-
 struct chip_operations northbridge_amd_pi_00730F01_ops = {
    CHIP_NAME("AMD FAM16 Root Complex")
-	.enable_dev = root_complex_enable_dev,
    .final = fam16_finalize,
 };