Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37754 )
Change subject: [WIP] AGESA,binaryPI: Set max p-state early ......................................................................
[WIP] AGESA,binaryPI: Set max p-state early
Change-Id: I99166e03f2580828c66305326f5141d956707f08 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/fixme.c M src/drivers/amd/agesa/bootblock.c 2 files changed, 10 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37754/1
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index c2e859e..2b412fa 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -92,10 +92,6 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ - MsrReg = 0; - LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); }
void amd_initenv(void) diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 3763b98..f45c9ab 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -28,6 +28,16 @@ OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); }
+#if 0 +/* for every core */ +static void max_pstate(void) +{ + /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ + MsrReg = 0; + LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); +} +#endif + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { enable_pci_mmconf();
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37754 )
Change subject: [WIP] AGESA,binaryPI: Set max p-state early ......................................................................
Patch Set 1:
At first glance no difference in timestamps (with console loglevel 0) on apu1.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37754 )
Change subject: [WIP] AGESA,binaryPI: Set max p-state early ......................................................................
Patch Set 1:
Patch Set 1:
At first glance no difference in timestamps (with console loglevel 0) on apu1.
Used: msr_t msr = { .hi = 0, .lo = 0 }; wrmsr(PS_CTL_REG, msr); of course
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37754
to look at the new patch set (#2).
Change subject: AGESA fam14: Remove early p-state setting ......................................................................
AGESA fam14: Remove early p-state setting
No improvement was measured with this applied.
Change-Id: I99166e03f2580828c66305326f5141d956707f08 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/fixme.c 1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37754/2
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37754 )
Change subject: AGESA fam14: Remove early p-state setting ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37754 )
Change subject: AGESA fam14: Remove early p-state setting ......................................................................
AGESA fam14: Remove early p-state setting
No improvement was measured with this applied.
Change-Id: I99166e03f2580828c66305326f5141d956707f08 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37754 Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/amd/agesa/family14/fixme.c 1 file changed, 0 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index c2e859e..2b412fa 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -92,10 +92,6 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ - MsrReg = 0; - LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); }
void amd_initenv(void)
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)