[M] Change in coreboot[master]: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params

[Werner Zeh (Code Review)]

Attention is currently required from: Michał Żygowski, Kacper Stojek, Lean Sheng Tan.

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72404 )

Change subject: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params
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Patch Set 2:

(1 comment)

File src/soc/intel/elkhartlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/72404/comment/ba4b1562_0343cd27 
PS2, Line 159: if (CONFIG_TTYS0_BASE == 0x3f8)
             : 			m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8;
             : 		else if (CONFIG_TTYS0_BASE == 0x2f8)
             : 			m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_2F8;
> So how do you suggest to handle them?

Looks like setting these parameters is added in this commit. Could you please either mention it in the commit message or (preferably) do it in a separate commit?