Change in coreboot[master]: soc/intel/tigerlake: Add Display related UPD configs for Jasper Lake
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39131 )
Change subject: soc/intel/tigerlake: Add Display related UPD configs for Jasper Lake ......................................................................
soc/intel/tigerlake: Add Display related UPD configs for Jasper Lake
Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39131/1
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index e6b5b58..d445f60 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -87,6 +87,13 @@
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+ /* Display */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + /* Audio */ m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0;
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39131 )
Change subject: soc/intel/tigerlake: Add Display related UPD configs for Jasper Lake ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39131/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39131/1//COMMIT_MSG@7 PS1, Line 7: Display display
https://review.coreboot.org/c/coreboot/+/39131/1//COMMIT_MSG@8 PS1, Line 8: Tested how?
Hello Patrick Rudolph, Karthik Ramasubramanian, Justin TerAvest, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39131
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Add display related UPD configs for Jasper Lake ......................................................................
soc/intel/tigerlake: Add display related UPD configs for Jasper Lake
TEST=Build dedede board
Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39131/2
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39131 )
Change subject: soc/intel/tigerlake: Add display related UPD configs for Jasper Lake ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39131/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39131/1//COMMIT_MSG@7 PS1, Line 7: Display
display
Done
https://review.coreboot.org/c/coreboot/+/39131/1//COMMIT_MSG@8 PS1, Line 8:
Tested how?
Done
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39131 )
Change subject: soc/intel/tigerlake: Add display related UPD configs for Jasper Lake ......................................................................
Patch Set 2: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39131 )
Change subject: soc/intel/tigerlake: Add display related UPD configs for Jasper Lake ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39131 )
Change subject: soc/intel/tigerlake: Add display related UPD configs for Jasper Lake ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39131 )
Change subject: soc/intel/tigerlake: Add display related UPD configs for Jasper Lake ......................................................................
soc/intel/tigerlake: Add display related UPD configs for Jasper Lake
TEST=Build dedede board
Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5 Signed-off-by: Aamir Bohra aamir.bohra@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39131 Reviewed-by: Karthik Ramasubramanian kramasub@google.com Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: V Sowmya v.sowmya@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 1 file changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved V Sowmya: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index e88d809..829e1e3 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -87,6 +87,13 @@
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+ /* Display */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + /* Audio */ m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0;
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Aamir Bohra (Code Review) -
Karthik Ramasubramanian (Code Review)
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Paul Menzel (Code Review)
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Subrata Banik (Code Review)
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V Sowmya (Code Review)