[XS] Change in coreboot[main]: soc/intel: seperate slp-s0 residency counter frequency in LPIT table

[Sukumar Ghorai (Code Review)]

Attention is currently required from: Jakub Czapiga, Paul Menzel, Subrata Banik.

Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78177?usp=email )

Change subject: soc/intel: seperate slp-s0 residency counter frequency in LPIT table
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Patch Set 4:

(5 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/78177/comment/aea0bb72_022595ec :
PS4, Line 9: Table(LPIT)
> Please add a space before the (.

Acknowledged

https://review.coreboot.org/c/coreboot/+/78177/comment/7afedd8a_7945e523 :
PS4, Line 12: read via memory mapped
> … IO?

Acknowledged

https://review.coreboot.org/c/coreboot/+/78177/comment/b08602b9_9fae5ad6 :
PS4, Line 14: https://www.uefi.org/sites/default/files/resources/
            : Intel_ACPI_Low_Power_S0_Idle.pdf
> The URL should be one line.

Acknowledged

https://review.coreboot.org/c/coreboot/+/78177/comment/0b91e1ba_970f2b79 :
PS4, Line 23:   cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
> What device? What do you check exactly? Before your patch it was 0?

Acknowledged

File src/soc/intel/common/block/acpi/lpit.c:

https://review.coreboot.org/c/coreboot/+/78177/comment/f14c1786_59c80eb4 :
PS4, Line 34: 	pkg_counter->counter_frequency			= 0; /* same freq as TSC */
> The macro is defined as 0. […]

Acknowledged