Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock - coreboot-gerrit

27 Jun 2019


      Steve Mooney has removed a vote on this change.
Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Removed Code-Review-1 by Steve Mooney (1002423)
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Gerrit-Change-Number: 25442
Gerrit-PatchSet: 14
Gerrit-Owner: Julien Viard de Galbert coreboot-review-ju@vdg.name
Gerrit-Reviewer: David Guckian david.guckian@intel.com
Gerrit-Reviewer: Julien Viard de Galbert coreboot-review-ju@vdg.name
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
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Gerrit-Reviewer: Steve Mooney
Gerrit-Reviewer: Vanny E vanessa.f.eusebio@intel.com
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Gerrit-CC: Jay Talbott JayTalbott@sysproconsulting.com
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