Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 )
Change subject: soc/intel/tigerlake: Update Kconfig ......................................................................
Patch Set 12:
(6 comments)
https://review.coreboot.org/c/coreboot/+/37426/2/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/37426/2/src/soc/intel/tigerlake/Kco... PS2, Line 64: select INTEL_CAR_NEM
Yes for now, NEM Enahanced mode boot is WIP. […]
Done
https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kco... PS8, Line 159: 0xfe03e000
Why was this changed?
Done
https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kco... PS8, Line 169: 0x7FFF
The change is in accordance with tigerlake FSP, I will find supporting doc if any.
It due to UART source clock change from 120MHz to 100MHz
https://review.coreboot.org/c/coreboot/+/37426/12/src/soc/intel/tigerlake/Kc... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/37426/12/src/soc/intel/tigerlake/Kc... PS12, Line 169: 0x25a
It based on below calculation […]
Done
https://review.coreboot.org/c/coreboot/+/37426/1/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/northbridge.asl:
https://review.coreboot.org/c/coreboot/+/37426/1/src/soc/intel/tigerlake/acp... PS1, Line 25: Name (_ADR, Zero) // _ADR: Address
Below are compile error. we should sue only one method (_HID or _ADR). […]
Done
https://review.coreboot.org/c/coreboot/+/37426/5/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/37426/5/src/soc/intel/tigerlake/inc... PS5, Line 21: void mainboard_fspm_params(FSPM_UPD *mupd);
need consistent spacing around '*' (ctx:WxV)
Done
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Wonkyu Kim (Code Review)