Change in coreboot[master]: mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller

[Werner Zeh (Code Review)]

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36676 )

Change subject: mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller
......................................................................

mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller

This mainboard variant uses SD-card and not eMMC. Therefore eMMC
controller is disabled while SDHCI is enabled.

Change-Id: I40b314905730b5d74c674d2251f8a4e5c807805f
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/36676/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index e1e79b4..6c18db9 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -97,8 +97,8 @@
    	device pci 19.1 off end	# - SPI 1
    	device pci 19.2 off end	# - SPI 2
    	device pci 1a.0 off end	# - PWM
-		device pci 1b.0 off end	# - SDCARD
-		device pci 1c.0 on  end	# - eMMC
+		device pci 1b.0 on  end	# - SDCARD
+		device pci 1c.0 off end	# - eMMC
    	device pci 1d.0 off end	# - UFS
    	device pci 1e.0 off end	# - SDIO
    	device pci 1f.0 on  end	# - LPC

[Mario Scheithauer (Code Review)]

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36676 )

Change subject: mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36676/1/src/mainboard/siemens/mc_ap... 
File src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/36676/1/src/mainboard/siemens/mc_ap... 
PS1, Line 45: 
            : 	# 0:HS400(Default), 1:HS200, 2:DDR50
            : 	register "emmc_host_max_speed" = "1"
if emmc is disabled, then this can actually removed and probably also the emmc entries above

[Mario Scheithauer (Code Review)]

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36676 )

Change subject: mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller
......................................................................

Patch Set 1: Code-Review+1

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36676 )

Change subject: mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36676/1/src/mainboard/siemens/mc_ap... 
File src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/36676/1/src/mainboard/siemens/mc_ap... 
PS1, Line 45: 
            : 	# 0:HS400(Default), 1:HS200, 2:DDR50
            : 	register "emmc_host_max_speed" = "1"
> if emmc is disabled, then this can actually removed and probably also the emmc entries above

Good point. Will remove the eMMC related entries.

[Werner Zeh (Code Review)]

Hello Mario Scheithauer, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36676

to look at the new patch set (#2).

Change subject: mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller
......................................................................

mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller

This mainboard variant uses SD-card and not eMMC. Therefore eMMC
controller is disabled while SDHCI is enabled.

Change-Id: I40b314905730b5d74c674d2251f8a4e5c807805f
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
1 file changed, 2 insertions(+), 34 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/36676/2

[Mario Scheithauer (Code Review)]

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36676 )

Change subject: mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36676 )

Change subject: mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller
......................................................................

mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller

This mainboard variant uses SD-card and not eMMC. Therefore eMMC
controller is disabled while SDHCI is enabled.

Change-Id: I40b314905730b5d74c674d2251f8a4e5c807805f
Signed-off-by: Werner Zeh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36676
Reviewed-by: Mario Scheithauer 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
1 file changed, 2 insertions(+), 34 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mario Scheithauer: Looks good to me, approved

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index e1e79b4..17b7fac 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -14,38 +14,6 @@
    register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
    register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"

-	# EMMC TX DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [14:8] steps of delay for HS400, each 125ps.
-	# [6:0] steps of delay for SDR104/HS200, each 125ps.
-	register "emmc_tx_data_cntl1" = "0x0C16"
-
-	# EMMC TX DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_tx_data_cntl2" = "0x28162828"
-
-	# EMMC RX CMD/DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
-
-	# EMMC RX CMD/DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [17:16] stands for Rx Clock before Output Buffer
-	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
-	# [6:0] steps of delay for HS200, each 125ps.
-	register "emmc_rx_cmd_data_cntl2" = "0x10008"
-
-	# 0:HS400(Default), 1:HS200, 2:DDR50
-	register "emmc_host_max_speed" = "1"
-
    device domain 0 on
    	device pci 00.0 on  end	# - Host Bridge
    	device pci 00.1 off end	# - DPTF
@@ -97,8 +65,8 @@
    	device pci 19.1 off end	# - SPI 1
    	device pci 19.2 off end	# - SPI 2
    	device pci 1a.0 off end	# - PWM
-		device pci 1b.0 off end	# - SDCARD
-		device pci 1c.0 on  end	# - eMMC
+		device pci 1b.0 on  end	# - SDCARD
+		device pci 1c.0 off end	# - eMMC
    	device pci 1d.0 off end	# - UFS
    	device pci 1e.0 off end	# - SDIO
    	device pci 1f.0 on  end	# - LPC