Change in coreboot[master]: soc/inte/alderlake: [TEST][PATCH 1/2] Enable hotplug and configure fr...

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sugnan Prabhu S, Sridhar Siricilla, Subrata Banik.
Hello build bot (Jenkins), Maulik V Vaghela, Rizwan Qureshi, Sugnan Prabhu S, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/52244

to look at the new patch set (#2).

Change subject: soc/inte/alderlake: [TEST][PATCH 1/2] Enable hotplug and configure free clock for PCIe RPs
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soc/inte/alderlake: [TEST][PATCH 1/2] Enable hotplug and configure free clock for PCIe RPs

The patch enables hotplug, places PCIe in compliance test mode and
Configures Clock sources to run free for EV test.

Signed-off-by: Sridhar Siricilla 
Change-Id: Ib5752bd1586e6062f740ca7a32df2135e26257b9
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 8 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/52244/2