Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45645 )
Change subject: soc/intel/jasperlake: Update VR Configuration Values ......................................................................
soc/intel/jasperlake: Update VR Configuration Values
This patch fixes the CPU Throttling issue observed on Drawlat
BRANCH=None BUG=b:167472333
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45645/1
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index cdd088e..6c83503 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -177,6 +177,10 @@ sizeof(params->SataPortsDevSlp)); }
+ /* VR Configuration */ + params->IccMax[0] = 140; + params->TdcCurrentLimit[0] = 80; + /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); params->ScsSdCardEnabled = is_dev_enabled(dev);
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45645 )
Change subject: soc/intel/jasperlake: Add VR Configuration settings ......................................................................
Patch Set 5: Code-Review+2
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45645 )
Change subject: soc/intel/jasperlake: Add VR Configuration settings ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45645/5/src/soc/intel/jasperlake/ch... File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/45645/5/src/soc/intel/jasperlake/ch... PS5, Line 140: uint32_t as per this https://review.coreboot.org/c/coreboot/+/45825/3/src/mainboard/google/dedede... : here range is 0-200, can you check appropriate data type uint8_t ?
https://review.coreboot.org/c/coreboot/+/45645/5/src/soc/intel/jasperlake/ch... PS5, Line 141: uint32_t https://review.coreboot.org/c/coreboot/+/45825/3/src/mainboard/google/dedede... : here range is 0-63999, can you check for this also appropriate data type uinit16_t might be enough ?
Hello build bot (Jenkins), Maulik V Vaghela, Sumeet R Pawnikar, Krishna P Bhat D, Aamir Bohra, Ronak Kanabar, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45645
to look at the new patch set (#6).
Change subject: soc/intel/jasperlake: Add VR Configuration settings ......................................................................
soc/intel/jasperlake: Add VR Configuration settings
This CL fixes the CPU Throttling issue.
BUG=b:167472333 TEST=Build and boot dedede and observe the slope and offset values getting updated in the fsp debug log
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45645/6
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45645 )
Change subject: soc/intel/jasperlake: Add VR Configuration settings ......................................................................
Patch Set 6:
(2 comments)
@Sumeet, Aligning with FSP and keeping it uint16 for both slope and offset.
https://review.coreboot.org/c/coreboot/+/45645/5/src/soc/intel/jasperlake/ch... File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/45645/5/src/soc/intel/jasperlake/ch... PS5, Line 140: uint32_t
as per this https://review.coreboot. […]
Ack
https://review.coreboot.org/c/coreboot/+/45645/5/src/soc/intel/jasperlake/ch... PS5, Line 141: uint32_t
Ack
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45645 )
Change subject: soc/intel/jasperlake: Add VR Configuration settings ......................................................................
Patch Set 6: Code-Review+2
Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45645 )
Change subject: soc/intel/jasperlake: Add VR Configuration settings ......................................................................
soc/intel/jasperlake: Add VR Configuration settings
This CL fixes the CPU Throttling issue.
BUG=b:167472333 TEST=Build and boot dedede and observe the slope and offset values getting updated in the fsp debug log
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 6b5f599..5a87a91 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -136,6 +136,10 @@ /* Heci related */ uint8_t Heci3Enabled;
+ /* VR Config Settings for IA Core */ + uint16_t ImonSlope; + uint16_t ImonOffset; + /* Gfx related */ uint8_t IgdDvmt50PreAlloc; uint8_t InternalGfx; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index d2e07e9..1919936 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -177,6 +177,10 @@ sizeof(params->SataPortsDevSlp)); }
+ /* VR Configuration */ + params->ImonSlope[0] = config->ImonSlope; + params->ImonOffset[0] = config->ImonOffset; + /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); params->ScsSdCardEnabled = is_dev_enabled(dev);
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Karthik Ramasubramanian (Code Review) -
Meera Ravindranath (Code Review)
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Sumeet R Pawnikar (Code Review)