Change in coreboot[master]: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47234 )

Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
......................................................................

sb/intel/lynxpoint: Correct SATA DTLE IOBP registers

Testing shows that these registers are backwards. Use the definitions
from Broadwell instead. All affected boards use the same value for both.

Change-Id: Ie47c9fddc2e9e15ce4c64821ea3a69356ac31b1a
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/lynxpoint/pch.h
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47234/1

diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 66cd05e..429dcc0 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -267,10 +267,10 @@
 /* SATA IOBP Registers */
 #define SATA_IOBP_SP0G3IR	0xea000151
 #define SATA_IOBP_SP1G3IR	0xea000051
-#define SATA_IOBP_SP0DTLE_DATA	0xea002550
-#define SATA_IOBP_SP0DTLE_EDGE	0xea002554
-#define SATA_IOBP_SP1DTLE_DATA	0xea002750
-#define SATA_IOBP_SP1DTLE_EDGE	0xea002754
+#define SATA_IOBP_SP0DTLE_DATA	0xea002750
+#define SATA_IOBP_SP0DTLE_EDGE	0xea002754
+#define SATA_IOBP_SP1DTLE_DATA	0xea002550
+#define SATA_IOBP_SP1DTLE_EDGE	0xea002554

#define SATA_DTLE_MASK		0xF
 #define SATA_DTLE_DATA_SHIFT	24

[Iru Cai (vimacs) (Code Review)]

Iru Cai (vimacs) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47234 )

Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
......................................................................

Patch Set 1:

What about LynxPoint-H?

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47234 )

Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
......................................................................

Patch Set 1:
> Patch Set 1:
>
> What about LynxPoint-H?

None of the boards in the tree use custom DTLE settings.

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47234 )

Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
......................................................................

Patch Set 1: Code-Review+2

(2 comments)

https://review.coreboot.org/c/coreboot/+/47234/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47234/1//COMMIT_MSG@9 
PS1, Line 9: Testing
Would be nice to elaborate on the testing. Could you break functionality
on a given port with a different value?

https://review.coreboot.org/c/coreboot/+/47234/1/src/southbridge/intel/lynxp... 
File src/southbridge/intel/lynxpoint/pch.h:

https://review.coreboot.org/c/coreboot/+/47234/1/src/southbridge/intel/lynxp... 
PS1, Line 275: #define SATA_DTLE_MASK		0xF
BIOS spec suggests this should be 0x3f

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47234 )

Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47234/1/src/southbridge/intel/lynxp... 
File src/southbridge/intel/lynxpoint/pch.h:

https://review.coreboot.org/c/coreboot/+/47234/1/src/southbridge/intel/lynxp... 
PS1, Line 275: #define SATA_DTLE_MASK		0xF
> BIOS spec suggests this should be 0x3f

Actually, it just says "AND mask" not if it relates to the values.

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47234 )

Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47234/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47234/1//COMMIT_MSG@9 
PS1, Line 9: Testing
> Would be nice to elaborate on the testing. Could you break functionality […]

It's what has been described here: https://review.coreboot.org/c/coreboot/+/45578/8/src/mainboard/hp/folio_9480...

Essentially, not applying the IOBP settings for "port 0" made port 1 stop working. I don't have any Haswell ULT board nearby I could test things on, however.

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47234 )

Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
......................................................................

sb/intel/lynxpoint: Correct SATA DTLE IOBP registers

Testing shows that these registers are backwards. Use the definitions
from Broadwell instead. All affected boards use the same value for both.

Change-Id: Ie47c9fddc2e9e15ce4c64821ea3a69356ac31b1a
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47234
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/southbridge/intel/lynxpoint/pch.h
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 66cd05e..429dcc0 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -267,10 +267,10 @@
 /* SATA IOBP Registers */
 #define SATA_IOBP_SP0G3IR	0xea000151
 #define SATA_IOBP_SP1G3IR	0xea000051
-#define SATA_IOBP_SP0DTLE_DATA	0xea002550
-#define SATA_IOBP_SP0DTLE_EDGE	0xea002554
-#define SATA_IOBP_SP1DTLE_DATA	0xea002750
-#define SATA_IOBP_SP1DTLE_EDGE	0xea002754
+#define SATA_IOBP_SP0DTLE_DATA	0xea002750
+#define SATA_IOBP_SP0DTLE_EDGE	0xea002754
+#define SATA_IOBP_SP1DTLE_DATA	0xea002550
+#define SATA_IOBP_SP1DTLE_EDGE	0xea002554

#define SATA_DTLE_MASK		0xF
 #define SATA_DTLE_DATA_SHIFT	24