Change in coreboot[master]: soc/amd/cezanne: add STT settings to deviectree

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52198 )

Change subject: soc/amd/cezanne: add STT settings to deviectree
......................................................................

soc/amd/cezanne: add STT settings to deviectree

Signed-off-by: Felix Held 
Change-Id: Ifbcc85cc10d59f1418bbf0ed4a0dc7549d589a26
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fsp_m_params.c
2 files changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/52198/1

diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index 317dd53..91fabac 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -14,6 +14,27 @@

uint8_t downcore_mode;
    uint8_t disable_smt;
+
+	uint8_t stt_control;
+	uint8_t stt_pcb_sensor_count;
+	uint16_t stt_min_limit;
+	uint16_t stt_m1;
+	uint16_t stt_m2;
+	uint16_t stt_m3;
+	uint16_t stt_m4;
+	uint16_t stt_m5;
+	uint16_t stt_m6;
+	uint16_t stt_c_apu;
+	uint16_t stt_c_gpu;
+	uint16_t stt_c_hs2;
+	uint16_t stt_alpha_apu;
+	uint16_t stt_alpha_gpu;
+	uint16_t stt_alpha_hs2;
+	uint16_t stt_skin_temp_apu;
+	uint16_t stt_skin_temp_gpu;
+	uint16_t stt_skin_temp_hs2;
+	uint16_t stt_error_coeff;
+	uint16_t stt_error_rate_coefficient;
 };

#endif /* CEZANNE_CHIP_H */
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index baf4ca8..cb9e97f 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -69,5 +69,27 @@
    mcfg->ccx_down_core_mode = config->downcore_mode;
    mcfg->ccx_disable_smt = config->disable_smt;

+	/* when stt_control isn't 1, FSP will ignore the other stt values */
+	mcfg->stt_control = config->stt_control;
+	mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count;
+	mcfg->stt_min_limit = config->stt_min_limit;
+	mcfg->stt_m1 = config->stt_m1;
+	mcfg->stt_m2 = config->stt_m2;
+	mcfg->stt_m3 = config->stt_m3;
+	mcfg->stt_m4 = config->stt_m4;
+	mcfg->stt_m5 = config->stt_m5;
+	mcfg->stt_m6 = config->stt_m6;
+	mcfg->stt_c_apu = config->stt_c_apu;
+	mcfg->stt_c_gpu = config->stt_c_gpu;
+	mcfg->stt_c_hs2 = config->stt_c_hs2;
+	mcfg->stt_alpha_apu = config->stt_alpha_apu;
+	mcfg->stt_alpha_gpu = config->stt_alpha_gpu;
+	mcfg->stt_alpha_hs2 = config->stt_alpha_hs2;
+	mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu;
+	mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu;
+	mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2;
+	mcfg->stt_error_coeff = config->stt_error_coeff;
+	mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient;
+
    fsp_fill_pcie_ddi_descriptors(mcfg);
 }