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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email )
Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config ......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
I based on the same upstream tip and pick your latest 2 changes: 77594/2 and 77557/3. They simply switch SAVE_MRC_AFTER_FSPS to MRC_STASH_TO_CBMEM but it doesn't work. Because from save_mrc_data.c, save_mrc_data() is moved to an earlier stage BS_PRE_DEVICE-ON_ENTRY which is before FSP-S is run, therefore it cannot find FSP_NON_VOLATILE_STORAGE_HOB and cannot stash it to cbmem:
[NOTE ] coreboot-4.21-120-gb394816b329c-dirty Fri Sep 01 05:31:26 UTC 2023 x86_32 ramstage starting (log level: 7)...[0m [INFO ] POST: 0x39[0m [INFO ] POST: 0x6f[0m [ERROR] FSP_NON_VOLATILE_STORAGE_HOB missing![0m [DEBUG] BS: BS_PRE_DEVICE entry times (exec / console): 0 / 23 ms[0m [INFO ] POST: 0x70[0m [DEBUG] BS: BS_PRE_DEVICE run times (exec / console): 0 / 6 ms[0m [INFO ] POST: 0x71[0m [DEBUG] coreboot: calling fsp_silicon_init[0m
At a later stage at BS_DEV_ENUMERATE, finalize_mrc_cache() tries to look for mrc data from cbmem but cannot find it: [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1348 / 4753 ms[0m [DEBUG] FMAP: area RW_MRC_CACHE found @ 3000000 (65536 bytes)[0m [INFO ] MRC: No data in cbmem for 'RW_MRC_CACHE'.
If I only still make save_mrc_data runs at BS_DEV_INIT_CHIPS, it can work on my 2S AC.
Please pick all 4 cls 1. CB:77594 2. CB:77594 3. CB:77556 4. CB:77295
I might need to change the patch order to fix the problem you have mentioned. But my understanding and debug says, after picking all 4 CLs, you shouldn't see any problem on 1S AC or 2S AC.
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Subrata Banik (Code Review)