Qizhong Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48138 )
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
HACK: Enable PCIe refclk 100M
Don't pull into TOT. Thanks. A temporary patch for PCIe compliance test. Set GPIO65 pinmux for PCIe function which is clkreq#.
Signed-off-by: mtk20626 qizhong.cheng@mediatek.com Change-Id: Ic4898a2b10c026a6d79b0f364c6a48e3f21c56ad --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/pcie.h A src/soc/mediatek/mt8192/pcie.c 3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48138/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 37aa5f1..fca5b83 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -57,6 +57,7 @@ ramstage-y += spm.c ramstage-y += sspm.c ramstage-y += ufs.c +ramstage-y += pcie.c ramstage-y += ../common/mtlib.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/include/soc/pcie.h b/src/soc/mediatek/mt8192/include/soc/pcie.h new file mode 100644 index 0000000..dd8f7ab --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pcie.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_PCIE_H +#define SOC_MEDIATEK_MT8192_PCIE_H + +void mtk_pcie_prepare(void); + +#endif diff --git a/src/soc/mediatek/mt8192/pcie.c b/src/soc/mediatek/mt8192/pcie.c new file mode 100644 index 0000000..d3e4213 --- /dev/null +++ b/src/soc/mediatek/mt8192/pcie.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/pcie.h> + +#define REG_PCIE_CLKREQ_EN (void *)(GPIO_BASE + 0x380) + +void mtk_pcie_prepare(void) +{ + u32 vaule; + + /* set PCIe clkreq# for refclk 100M */ + vaule = read32(REG_PCIE_CLKREQ_EN); + write32(REG_PCIE_CLKREQ_EN, vaule | 0x33); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48138 )
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48138/1/src/soc/mediatek/mt8192/pci... File src/soc/mediatek/mt8192/pcie.c:
https://review.coreboot.org/c/coreboot/+/48138/1/src/soc/mediatek/mt8192/pci... PS1, Line 11: u32 vaule; 'vaule' may be misspelled - perhaps 'value'?
https://review.coreboot.org/c/coreboot/+/48138/1/src/soc/mediatek/mt8192/pci... PS1, Line 14: vaule = read32(REG_PCIE_CLKREQ_EN); 'vaule' may be misspelled - perhaps 'value'?
https://review.coreboot.org/c/coreboot/+/48138/1/src/soc/mediatek/mt8192/pci... PS1, Line 15: write32(REG_PCIE_CLKREQ_EN, vaule | 0x33); 'vaule' may be misspelled - perhaps 'value'?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48138
to look at the new patch set (#2).
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
HACK: Enable PCIe refclk 100M
Don't pull into TOT. Thanks. A temporary patch for PCIe compliance test. Set GPIO65 pinmux for PCIe function which is clkreq#.
Signed-off-by: mtk20626 qizhong.cheng@mediatek.com Change-Id: Ic4898a2b10c026a6d79b0f364c6a48e3f21c56ad --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/pcie.h A src/soc/mediatek/mt8192/pcie.c 3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48138/2
Qizhong Cheng has removed Patrick Georgi from this change. ( https://review.coreboot.org/c/coreboot/+/48138 )
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
Removed reviewer Patrick Georgi.
Qizhong Cheng has removed Martin Roth from this change. ( https://review.coreboot.org/c/coreboot/+/48138 )
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
Removed reviewer Martin Roth.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48138
to look at the new patch set (#3).
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
HACK: Enable PCIe refclk 100M
Don't pull into TOT. Thanks. This patch is just to open the refclk of pcie during the coreboot stage for PCIe hardware compliance testing. If Alvis wants to continue testing pcie hardware, please cherry-pick the patch.. Set GPIO65 pinmux for PCIe function which is clkreq#.
Signed-off-by: mtk20626 qizhong.cheng@mediatek.com Change-Id: Ic4898a2b10c026a6d79b0f364c6a48e3f21c56ad --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/pcie.h A src/soc/mediatek/mt8192/pcie.c 3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48138/3
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48138
to look at the new patch set (#4).
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
HACK: Enable PCIe refclk 100M
Don't pull into TOT. Thanks. b/170703028 This patch is just to open the refclk of pcie during the coreboot stage for PCIe hardware compliance testing. If Alvis wants to continue to test pcie hardware, please cherry-pick the patch. Set GPIO65 pinmux for PCIe function which is clkreq#.
Signed-off-by: mtk20626 qizhong.cheng@mediatek.com Change-Id: Ic4898a2b10c026a6d79b0f364c6a48e3f21c56ad --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/pcie.h A src/soc/mediatek/mt8192/pcie.c 3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48138/4
Qizhong Cheng has removed Martin Roth from this change. ( https://review.coreboot.org/c/coreboot/+/48138 )
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
Removed reviewer Martin Roth.
Qizhong Cheng has removed Patrick Georgi from this change. ( https://review.coreboot.org/c/coreboot/+/48138 )
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
Removed reviewer Patrick Georgi.
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48138?usp=email )
Change subject: HACK: Enable PCIe refclk 100M ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
build bot (Jenkins) (Code Review) -
Martin L Roth (Code Review)
-
Qizhong Cheng (Code Review)