cedarhouse1@comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add STM Support ......................................................................
soc/intel: Add STM Support
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers edmyers@tycho.nsa.gov --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pmutil.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c 14 files changed, 67 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37990/1
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d0b0421..22e414c 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -250,4 +250,7 @@
void enable_pm_timer_emulation(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 559adad..972314d 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -246,3 +246,10 @@
return rtc_failure; } + +/* STM Support */ + +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 18004fa..c9074d8 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -155,4 +155,7 @@ /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 00db615..c049201 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -458,3 +458,10 @@
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} +} diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 5b85e74..356f0bc 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -172,5 +172,8 @@ /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index aded9c0..81fcb09 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -272,3 +272,10 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ + +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 44888ec..34c32a9 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -171,5 +171,8 @@ /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 7b6168b..440efd0 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -271,3 +271,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index ffcd91f..95b88ff 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -104,3 +104,11 @@ printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl);
} + +uint16_t get_pmbase(void) +{ + struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) + & B_QNC_LPC_PM1BLK_MASK; +} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index a3fb02f..e02b8a2 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -27,4 +27,7 @@ struct chipset_power_state *get_power_state(void); int fill_power_state(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 18b0c15..007d29c 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -197,4 +197,7 @@ return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS)); }
+/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 2b2141b..afe9b71 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -275,3 +275,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index fb9b67b..d2f47e2 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -177,5 +177,7 @@ /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void);
+/* STM Support */ +uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 39734bb..19edeb3 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -279,3 +279,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +}
cedarhouse1@comcast.net has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add STM Support ......................................................................
Patch Set 1:
The large CL has now been spit into two: (1) the basic STM setup code (security/intel/stm) and (2) soc/intel where get_pmbase was added to platforms that did not have it
Hello Kyösti Mälkki, Werner Zeh, Aaron Durbin, Patrick Rudolph, Sumeet R Pawnikar, Christian Walter, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37990
to look at the new patch set (#2).
Change subject: soc/intel: Add STM Support ......................................................................
soc/intel: Add STM Support
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers edmyers@tycho.nsa.gov --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pmutil.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c 14 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37990/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add STM Support ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/37990/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37990/2//COMMIT_MSG@7 PS2, Line 7: soc/intel: Add STM Support that's not a good summary. better one would be: soc/intel: Add get_pmbase
cedarhouse1@comcast.net has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add STM Support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37990/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37990/2//COMMIT_MSG@7 PS2, Line 7: soc/intel: Add STM Support
that's not a good summary. better one would be: […]
changed as requested
Hello Kyösti Mälkki, Werner Zeh, Patrick Rudolph, Aaron Durbin, Sumeet R Pawnikar, Christian Walter, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37990
to look at the new patch set (#3).
Change subject: soc/intel: Add get_pmbase ......................................................................
soc/intel: Add get_pmbase
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers edmyers@tycho.nsa.gov --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pmutil.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c 14 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37990/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add get_pmbase ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37990/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37990/3//COMMIT_MSG@14 PS3, Line 14: SMI handler in SMI handlers it does not seem like a good idea to use a hardcoded value, but to use the one fetched from registers as it might be changed later on.
cedarhouse1@comcast.net has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add get_pmbase ......................................................................
Patch Set 3:
(1 comment)
This response generally deals with how the STM handles with changes in access.
If there are any questions on this response, please let me know.
https://review.coreboot.org/c/coreboot/+/37990/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37990/3//COMMIT_MSG@14 PS3, Line 14: SMI handler
in SMI handlers it does not seem like a good idea to use a hardcoded value, but to use the one fetch […]
Short answer - the pmbase can be changed later but you might have to tell the STM to allow access.
Long answer - As noted in the commit message, this value has to be in the BIOS resource so that the STM will allow the SMI handler to access the location represented by the pmbase value.
If the pmbase value is changed and the SMI Handler attempts to access this area, there are three possible scenarios: (1) the resource is claimed by the BIOS, (2) the resource is claimed by the OS and (3) the resource is unclaimed by either the BIOS or the OS.
(1) Since the BIOS has claimed the area, the attempted access by the SMI handler is allowed.
(2) If the O/S has claimed the area and has restricted access such that the SMI hander cannot access the area, then bad things happen as the SMI handler will not be allowed access. In the instance, if the OS changes the pmbase then it needs to tell the STM that the SMI handler is allowed access to this new area. NOTE: the O/S implementer should have gotten this correct during testing.
(3) If the resource is unclaimed, then the STM will grant the access to the SMI handler and generate a log message that the event happened.
Review: the BIOS resource list is the set of resources that the BIOS is claiming for the SMI handler. The operating system can also tell the STM the resources that it does not want the SMI handler to access. However, the operating system cannot override the list that the BIOS has generated. In the case of a conflict, the STM will generate an error message concerning the conflict giving the OS implementer, etc. a chance of deal with the conflict. Finally, the SMI handler is granted access to any resources that have not been claimed by the OS.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add get_pmbase ......................................................................
Patch Set 3: Code-Review+2
The pmbar should be locked at end of post, so using the define might be safe.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add get_pmbase ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/apollolake/pm... File src/soc/intel/apollolake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/apollolake/pm... PS3, Line 251: No blank line.
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/quark/acpi.c File src/soc/intel/quark/acpi.c:
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/quark/acpi.c@... PS3, Line 113: & B_QNC_LPC_PM1BLK_MASK; Do both lines fit into 96 character line?
cedarhouse1@comcast.net has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add get_pmbase ......................................................................
Patch Set 3:
(2 comments)
Will issue a new patch set once I get the smm_segs.h issue resolved.
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/apollolake/pm... File src/soc/intel/apollolake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/apollolake/pm... PS3, Line 251:
No blank line.
Done
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/quark/acpi.c File src/soc/intel/quark/acpi.c:
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/quark/acpi.c@... PS3, Line 113: & B_QNC_LPC_PM1BLK_MASK;
Do both lines fit into 96 character line?
No. The first line of code is 101 characters and the second is 92 characters.
So far during the early part of the review the BOT has been complaining when any line of code is over 80 characters. So, I made a big effort to ensure that everything is under 80 lines.
Is this a change?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add get_pmbase ......................................................................
Patch Set 3: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/cannonlake/pm... File src/soc/intel/cannonlake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/cannonlake/pm... PS3, Line 277: Please, no blank line here either.
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/quark/acpi.c File src/soc/intel/quark/acpi.c:
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/quark/acpi.c@... PS3, Line 113: & B_QNC_LPC_PM1BLK_MASK;
No. The first line of code is 101 characters and the second is 92 characters. […]
It was changed to 96 characters at some point.
Hello Kyösti Mälkki, Werner Zeh, Patrick Rudolph, Aaron Durbin, Sumeet R Pawnikar, Angel Pons, Christian Walter, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37990
to look at the new patch set (#4).
Change subject: soc/intel: Add get_pmbase ......................................................................
soc/intel: Add get_pmbase
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers edmyers@tycho.nsa.gov --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pmutil.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c 14 files changed, 63 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37990/4
cedarhouse1@comcast.net has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add get_pmbase ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/apollolake/pm... File src/soc/intel/apollolake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/apollolake/pm... PS3, Line 251:
Done
Done
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/cannonlake/pm... File src/soc/intel/cannonlake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/cannonlake/pm... PS3, Line 277:
Please, no blank line here either.
Done
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/quark/acpi.c File src/soc/intel/quark/acpi.c:
https://review.coreboot.org/c/coreboot/+/37990/3/src/soc/intel/quark/acpi.c@... PS3, Line 113: & B_QNC_LPC_PM1BLK_MASK;
It was changed to 96 characters at some point.
changed the second line to comply
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add get_pmbase ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37990 )
Change subject: soc/intel: Add get_pmbase ......................................................................
soc/intel: Add get_pmbase
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers edmyers@tycho.nsa.gov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990 Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pmutil.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c 14 files changed, 63 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d0b0421..22e414c 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -250,4 +250,7 @@
void enable_pm_timer_emulation(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 559adad..8151afc 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -246,3 +246,9 @@
return rtc_failure; } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 18004fa..c9074d8 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -155,4 +155,7 @@ /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 00db615..2445dfa 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -458,3 +458,9 @@
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 5b85e74..356f0bc 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -172,5 +172,8 @@ /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index aded9c0..2d691ad 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -272,3 +272,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 44888ec..34c32a9 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -171,5 +171,8 @@ /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 7b6168b..440efd0 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -271,3 +271,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index ffcd91f..5006b19 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -104,3 +104,10 @@ printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl);
} + +uint16_t get_pmbase(void) +{ + struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; +} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index a3fb02f..e02b8a2 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -27,4 +27,7 @@ struct chipset_power_state *get_power_state(void); int fill_power_state(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 18b0c15..007d29c 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -197,4 +197,7 @@ return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS)); }
+/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 2b2141b..afe9b71 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -275,3 +275,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index fb9b67b..d2f47e2 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -177,5 +177,7 @@ /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void);
+/* STM Support */ +uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 84a93ae..d9eb186 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -279,3 +279,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +}
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