Change in coreboot[master]: soc/intel/apollolake: Improve cold boot and S3 resume

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/29363

Change subject: soc/intel/apollolake: Improve cold boot and S3 resume
......................................................................

soc/intel/apollolake: Improve cold boot and S3 resume

FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure
PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default
100ms to 10ms to improve cold boot and S3 resume performance.

BUG=b:118676361
CQ-DEPEND=CL:*703187
TEST=Verified booting to kernel.

Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409
Signed-off-by: John Zhao 
---
M src/soc/intel/apollolake/chip.c
M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
2 files changed, 17 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29363/1

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 9ee6dbb..976c45a 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -567,6 +567,15 @@
     * has set up. Hence skipping in FSP.
     */
    silconfig->SkipSpiPCP = 1;
+
+	/*
+	 * FSP provides UPD interface to execute IPC command. In order to improve boot
+	 * performance, configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay
+	 * from 100ms (default) to 10ms.
+	 * PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms,
+	 *		    101=50ms, 110=75ms, 111=100ms (default)
+	 */
+	silconfig->PmicPmcIpcCtrl = 2;
 #endif
 }

diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
index cc194b2..e8d02c7 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
@@ -1715,9 +1715,15 @@
 **/
   UINT8                       SkipSpiPCP;

-/** Offset 0x03AB
+/** Offset 0x03AB - PMIC PCH_WROK delay configuration - IPC Configuration
+  Upd for changing PCH_WROK delay configuration : I2C_Slave_Address (31:23) + Register_Offset
+  (23:16) + OR Value (15:8) + AND Value (7:0)
 **/
-  UINT8                       ReservedFspsUpd[5];
+  UINT32                      PmicPmcIpcCtrl;
+
+/** Offset 0x03AF
+**/
+  UINT8                       ReservedFspsUpd[1];
 } FSP_S_CONFIG;

/** Fsp S SGX Configuration