Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40269 )
Change subject: mb/intel/tglrvp : Enable RP LTR ......................................................................
mb/intel/tglrvp : Enable RP LTR
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/40269/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 6cef4f8..5e43fc7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -45,6 +45,12 @@ register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1"
+ # Enable RP LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c5cc800..793c310 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -45,6 +45,12 @@ register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1"
+ # Enable PR LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1"
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40269 )
Change subject: mb/intel/tglrvp : Enable RP LTR ......................................................................
Patch Set 1: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40269 )
Change subject: mb/intel/tglrvp : Enable RP LTR ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40269 )
Change subject: mb/intel/tglrvp : Enable RP LTR ......................................................................
mb/intel/tglrvp : Enable RP LTR
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269 Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 12 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Srinidhi N Kaushik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 501aa2a..82303c6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -45,6 +45,12 @@ register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1"
+ # Enable RP LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 81d52a8..043185b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -45,6 +45,12 @@ register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1"
+ # Enable PR LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1"
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Patrick Georgi (Code Review) -
Srinidhi N Kaushik (Code Review)
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Wonkyu Kim (Code Review)