[S] Change in coreboot[master]: soc/intel/common: Update comment on HFSTS1.spi_protection_mode

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik, Tim Wawrzynczak.

Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/67533

to look at the new patch set (#2).

Change subject: soc/intel/common: Update comment on HFSTS1.spi_protection_mode
......................................................................

soc/intel/common: Update comment on HFSTS1.spi_protection_mode

The patch updates comment on HFSTS1.spi_protection_mode.
The spi_protection_mode indicates SPI protection status as well as EOM
status (in a single staged EOM flow). Starting from TGL platform, staged
EOM flow is introduced. In this flow, spi_protection_mode alone doesn't
indicate the EOM status.

For information on EOM status, please refer secton# 3.6.1 in doc#
612229.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla 
Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 28 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/67533/2