Change in coreboot[master]: soc/intel/common: Calculate and configure SF Mask 2

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56717 )

Change subject: soc/intel/common: Calculate and configure SF Mask 2
......................................................................

soc/intel/common: Calculate and configure SF Mask 2

As per TGL EDS, two ways will be controlled with one bit of SF QoS
register hence, this patch introduces SF_MASK_2WAYS_PER_BIT Kconfig to
allow SoC users to select SF_MASK_2WAYS_PER_BIT to follow the EDS
recommendation.

Calculate SF masks 2:
1. if CONFIG_SF_MASK_2WAYS_PER_BIT:
        a. data_ways = data_ways / 2

Also, program SF Mask#2 using below logic:
2. Set SF_MASK_2 = (1 << data_ways) - 1

Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56717
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/include/cpu/x86/msr.h
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
3 files changed, 35 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 26f1dcb..9e7e6fd 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -88,6 +88,8 @@
 #define IA32_HWP_CAPABILITIES		0x771
 #define IA32_HWP_REQUEST		0x774
 #define IA32_HWP_STATUS			0x777
+#define IA32_SF_QOS_INFO		0xc87
+#define  IA32_SF_WAY_COUNT_MASK		0x3f
 #define IA32_PQR_ASSOC			0xc8f
 /* MSR bits 33:32 encode slot number 0-3 */
 #define  IA32_PQR_ASSOC_MASK		(1 << 0 | 1 << 1)
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 16844d9..f02af1f 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -63,6 +63,14 @@
      IA32_L3_SF_MASK_x programming is required along with the data ways.
      This is applicable for TGL and beyond.

+config SF_MASK_2WAYS_PER_BIT
+	bool
+	depends on INTEL_CAR_NEM_ENHANCED
+	help
+	  In the case of non-inclusive cache architecture when two ways in
+	  the SF mask are controlled by one bit of the SF QoS register.
+	  This is applicable for TGL alone.
+
 config COS_MAPPED_TO_MSB
    bool
    depends on INTEL_CAR_NEM_ENHANCED
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 5f39507..e82406e 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -499,6 +499,7 @@
     * of RW data.
     */
    movl	$0x01, %eax
+	mov	%eax, %edx /* back up data_ways in edx */
    cmp	$CONFIG_DCACHE_RAM_SIZE, %ecx
    jnc	set_eviction_mask

@@ -508,6 +509,7 @@
     */
    mov	$CONFIG_DCACHE_RAM_SIZE, %eax
    div	%ecx
+	mov	%eax, %edx /* back up data_ways in edx */
    mov	%eax, %ecx
    movl	$0x01, %eax
    shl	%cl, %eax
@@ -517,6 +519,29 @@
    mov	%ebx, %edi /* back up number of ways */
    mov	%eax, %esi /* back up the non-eviction mask */
 #if CONFIG(CAR_HAS_SF_MASKS)
+	mov	%edx, %eax /* restore data_ways in eax */
+	/*
+	 * Calculate SF masks 2:
+	 * 1. if CONFIG_SF_MASK_2WAYS_PER_BIT: data_ways = data_ways / 2
+	 * 2. Program MSR 0x1892 Non-Eviction Mask #2
+	 *    IA32_CR_SF_QOS_MASK_2 = ((1 << data_ways) - 1)
+	 */
+#if CONFIG(SF_MASK_2WAYS_PER_BIT)
+	cmp	$0x01, %eax /* Skip Step 1 if data_ways = 1 */
+	jz	program_sf2
+	movl	$0x01, %ecx /* Step 1 */
+	shr	%cl, %eax
+#endif
+	/* Step 2 */
+	mov	%eax, %ecx
+	movl	$0x01, %eax
+	shl	%cl, %eax
+	subl	$0x01, %eax
+program_sf2:
+	xorl	%edx, %edx
+	mov	$IA32_CR_SF_QOS_MASK_2, %ecx
+	wrmsr
+
    /*
     * SF mask is programmed with the double number of bits than
     * the number of ways