Change in coreboot[master]: [WIP]drivers/aspeed: Add AST2500 support

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: [WIP]drivers/aspeed: Add AST2500 support
......................................................................

[WIP]drivers/aspeed: Add AST2500 support

Untested on AST2500.
Code for AST2400 still works.

TODO: Adjust Copyright.

Copy code from GNU/Linux kernel to coreboot to add AST2500 support.

Change-Id: I25bd34dd52a0acd3e04fc5818e011215ef907fad
Signed-off-by: Patrick Rudolph 
---
M src/drivers/aspeed/common/ast_dp501.c
M src/drivers/aspeed/common/ast_dram_tables.h
M src/drivers/aspeed/common/ast_drv.h
M src/drivers/aspeed/common/ast_post.c
M src/drivers/aspeed/common/ast_tables.h
5 files changed, 656 insertions(+), 170 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/34793/1

diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c
index 2e8b897..4b867c0 100644
--- a/src/drivers/aspeed/common/ast_dp501.c
+++ b/src/drivers/aspeed/common/ast_dp501.c
@@ -145,7 +145,7 @@
    return false;
 }

-bool ast_launch_m68k(struct drm_device *dev)
+static bool ast_launch_m68k(struct drm_device *dev)
 {
    struct ast_private *ast = dev->dev_private;
    u32 i, data, len = 0;
@@ -159,7 +159,10 @@
    	if (ast->dp501_fw_addr) {
    		fw_addr = ast->dp501_fw_addr;
    		len = 32*1024;
-		} else if (ast->dp501_fw) {
+		} else {
+			if (!ast->dp501_fw)
+				return false;
+
    		fw_addr = (u8 *)ast->dp501_fw->data;
    		len = ast->dp501_fw->size;
    	}
@@ -224,11 +227,7 @@

/* Read Link Capability */
    offset  = 0xf014;
-	data = ast_mindwm(ast, boot_address + offset);
-	linkcap[0] = (data & 0xff000000) >> 24;
-	linkcap[1] = (data & 0x00ff0000) >> 16;
-	linkcap[2] = (data & 0x0000ff00) >> 8;
-	linkcap[3] = (data & 0x000000ff);
+	*(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
    if (linkcap[2] == 0) {
    	linkrate = linkcap[0];
    	linklanes = linkcap[1];
diff --git a/src/drivers/aspeed/common/ast_dram_tables.h b/src/drivers/aspeed/common/ast_dram_tables.h
index 1d46ca6..986b2c9 100644
--- a/src/drivers/aspeed/common/ast_dram_tables.h
+++ b/src/drivers/aspeed/common/ast_dram_tables.h
@@ -158,4 +158,66 @@
    { 0xffff, 0xffffffff },
 };

+/*
+ * AST2500 DRAM settings modules
+ */
+#define REGTBL_NUM		17
+#define REGIDX_010		0
+#define REGIDX_014		1
+#define REGIDX_018		2
+#define REGIDX_020		3
+#define REGIDX_024		4
+#define REGIDX_02C		5
+#define REGIDX_030		6
+#define REGIDX_214		7
+#define REGIDX_2E0		8
+#define REGIDX_2E4		9
+#define REGIDX_2E8		10
+#define REGIDX_2EC		11
+#define REGIDX_2F0		12
+#define REGIDX_2F4		13
+#define REGIDX_2F8		14
+#define REGIDX_RFC		15
+#define REGIDX_PLL		16
+
+static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
+	0x64604D38,			/* 0x010 */
+	0x29690599,			/* 0x014 */
+	0x00000300,			/* 0x018 */
+	0x00000000,			/* 0x020 */
+	0x00000000,			/* 0x024 */
+	0x02181E70,			/* 0x02C */
+	0x00000040,			/* 0x030 */
+	0x00000024,			/* 0x214 */
+	0x02001300,			/* 0x2E0 */
+	0x0E0000A0,			/* 0x2E4 */
+	0x000E001B,			/* 0x2E8 */
+	0x35B8C105,			/* 0x2EC */
+	0x08090408,			/* 0x2F0 */
+	0x9B000800,			/* 0x2F4 */
+	0x0E400A00,			/* 0x2F8 */
+	0x9971452F,			/* tRFC  */
+	0x000071C1			/* PLL   */
+	};
+
+	static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
+	0x63604E37,			/* 0x010 */
+	0xE97AFA99,			/* 0x014 */
+	0x00019000,			/* 0x018 */
+	0x08000000,			/* 0x020 */
+	0x00000400,			/* 0x024 */
+	0x00000410,			/* 0x02C */
+	0x00000101,			/* 0x030 */
+	0x00000024,			/* 0x214 */
+	0x03002900,			/* 0x2E0 */
+	0x0E0000A0,			/* 0x2E4 */
+	0x000E001C,			/* 0x2E8 */
+	0x35B8C106,			/* 0x2EC */
+	0x08080607,			/* 0x2F0 */
+	0x9B000900,			/* 0x2F4 */
+	0x0E400A00,			/* 0x2F8 */
+	0x99714545,			/* tRFC  */
+	0x000071C1			/* PLL   */
+	};
+
 #endif
diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h
index 53640f1..e2904c2 100644
--- a/src/drivers/aspeed/common/ast_drv.h
+++ b/src/drivers/aspeed/common/ast_drv.h
@@ -44,6 +44,7 @@
    AST2150,
    AST2300,
    AST2400,
+	AST2500,
    AST1180,
 };

@@ -60,6 +61,7 @@
 #define AST_DRAM_1Gx32   3
 #define AST_DRAM_2Gx16   6
 #define AST_DRAM_4Gx16   7
+#define AST_DRAM_8Gx16   8

struct ast_fbdev;

@@ -213,11 +215,10 @@
 u32 ast_mindwm(struct ast_private *ast, u32 r);
 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
 /* ast dp501 */
-int ast_load_dp501_microcode(struct drm_device *dev);
 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
-bool ast_launch_m68k(struct drm_device *dev);
 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
 u8 ast_get_dp501_max_clk(struct drm_device *dev);
 void ast_init_3rdtx(struct drm_device *dev);
+void ast_release_firmware(struct drm_device *dev);
 #endif
diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c
index 5f935b9..dc825b5 100644
--- a/src/drivers/aspeed/common/ast_post.c
+++ b/src/drivers/aspeed/common/ast_post.c
@@ -34,7 +34,8 @@
 #include "ast_drv.h"
 #include "ast_dram_tables.h"

-static void ast_init_dram_2300(struct drm_device *dev);
+static void ast_post_chip_2300(struct drm_device *dev);
+static void ast_post_chip_2500(struct drm_device *dev);

void ast_enable_vga(struct drm_device *dev)
 {
@@ -61,13 +62,9 @@
    	/* TODO 1180 */
    } else {
    	ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
-		if (ch) {
-			ast_open_key(ast);
-			ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff);
-			return ch & 0x04;
-		}
+		return !!(ch & 0x01);
    }
-	return 0;
+	return false;
 }

static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
@@ -86,10 +83,11 @@
    uint8_t revision = data & 0xff;

/* reset scratch */
-	for (i = 0x81; i <= 0x8f; i++)
+	for (i = 0x81; i <= 0x9f; i++)
    	ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);

-	if (ast->chip == AST2300 || ast->chip == AST2400) {
+	if (ast->chip == AST2300 || ast->chip == AST2400 ||
+	    ast->chip == AST2500) {
    	if (revision >= 0x20)
    		ext_reg_info = extreginfo_ast2300;
    	else
@@ -113,7 +111,8 @@

/* Enable RAMDAC for A1 */
    reg = 0x04;
-	if (ast->chip == AST2300 || ast->chip == AST2400)
+	if (ast->chip == AST2300 || ast->chip == AST2400 ||
+	    ast->chip == AST2500)
    	reg |= 0x20;
    ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
 }
@@ -394,12 +393,14 @@
    pci_write_config_dword(ast->dev->pdev, 0x04, reg);

ast_enable_vga(dev);
-	ast_enable_mmio(dev);
    ast_open_key(ast);
+	ast_enable_mmio(dev);
    ast_set_def_ext_reg(dev);

-	if (ast->chip == AST2300 || ast->chip == AST2400)
-		ast_init_dram_2300(dev);
+	if (ast->chip == AST2500)
+		ast_post_chip_2500(dev);
+	else if (ast->chip == AST2300 || ast->chip == AST2400)
+		ast_post_chip_2300(dev);
    else
    	ast_init_dram_reg(dev);

@@ -459,87 +460,72 @@
    0x7C61D253
 };

-static int mmc_test_burst(struct ast_private *ast, u32 datagen)
+static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
 {
    u32 data, timeout;

ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
-	timeout = 0;
-	do {
-		data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
-		if (data & 0x2000) {
-			return 0;
-		}
-		if (++timeout > TIMEOUT) {
-			ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-			return 0;
-		}
-	} while (!data);
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	return 1;
-}
-
-static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
-{
-	u32 data, timeout;
-
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
-	timeout = 0;
-	do {
-		data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
-		if (++timeout > TIMEOUT) {
-			ast_moutdwm(ast, 0x1e6e0070, 0x0);
-			return -1;
-		}
-	} while (!data);
-	data = ast_mindwm(ast, 0x1e6e0078);
-	data = (data | (data >> 16)) & 0xffff;
-	ast_moutdwm(ast, 0x1e6e0070, 0x0);
-	return data;
-}
-
-static int mmc_test_single(struct ast_private *ast, u32 datagen)
-{
-	u32 data, timeout;
-
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
+	ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
    timeout = 0;
    do {
    	data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
    	if (data & 0x2000)
-			return 0;
+			return false;
    	if (++timeout > TIMEOUT) {
-			ast_moutdwm(ast, 0x1e6e0070, 0x0);
-			return 0;
+			ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
+			return false;
    	}
    } while (!data);
    ast_moutdwm(ast, 0x1e6e0070, 0x0);
-	return 1;
+	return true;
 }

-static int mmc_test_single2(struct ast_private *ast, u32 datagen)
+static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
 {
    u32 data, timeout;

ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
+	ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
    timeout = 0;
    do {
    	data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
    	if (++timeout > TIMEOUT) {
    		ast_moutdwm(ast, 0x1e6e0070, 0x0);
-			return -1;
+			return 0xffffffff;
    	}
    } while (!data);
    data = ast_mindwm(ast, 0x1e6e0078);
    data = (data | (data >> 16)) & 0xffff;
-	ast_moutdwm(ast, 0x1e6e0070, 0x0);
+	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
    return data;
 }

+
+static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test(ast, datagen, 0xc1);
+}
+
+static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test2(ast, datagen, 0x41);
+}
+
+static bool mmc_test_single(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test(ast, datagen, 0xc5);
+}
+
+static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test2(ast, datagen, 0x05);
+}
+
+static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test(ast, datagen, 0x85);
+}
+
 static int cbr_test(struct ast_private *ast)
 {
    u32 data;
@@ -615,16 +601,16 @@
    return data2;
 }

-static u32 cbr_test3(struct ast_private *ast)
+static bool cbr_test3(struct ast_private *ast)
 {
    if (!mmc_test_burst(ast, 0))
-		return 0;
+		return false;
    if (!mmc_test_single(ast, 0))
-		return 0;
-	return 1;
+		return false;
+	return true;
 }

-static u32 cbr_scan3(struct ast_private *ast)
+static bool cbr_scan3(struct ast_private *ast)
 {
    u32 patcnt, loop;

@@ -635,9 +621,9 @@
    			break;
    	}
    	if (loop == 2)
-			return 0;
+			return false;
    }
-	return 1;
+	return true;
 }

static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
@@ -1661,7 +1647,7 @@

}

-static void ast_init_dram_2300(struct drm_device *dev)
+static void ast_post_chip_2300(struct drm_device *dev)
 {
    struct ast_private *ast = dev->dev_private;
    struct ast2300_dram_param param;
@@ -1746,11 +1732,409 @@
    }

/* wait ready */
-	timeout = 0;
    do {
    	reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
-		timeout++;
-	} while (((reg & 0x40) == 0) && (timeout < COREBOOT_AST_FAILOVER_TIMEOUT));
-	if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT)
-		dev_err(dev->pdev, "Timeout while waiting for register\n");
+	} while ((reg & 0x40) == 0);
+}
+
+static bool cbr_test_2500(struct ast_private *ast)
+{
+	ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
+	ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
+	if (!mmc_test_burst(ast, 0))
+		return false;
+	if (!mmc_test_single_2500(ast, 0))
+		return false;
+	return true;
+}
+
+static bool ddr_test_2500(struct ast_private *ast)
+{
+	ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
+	ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
+	if (!mmc_test_burst(ast, 0))
+		return false;
+	if (!mmc_test_burst(ast, 1))
+		return false;
+	if (!mmc_test_burst(ast, 2))
+		return false;
+	if (!mmc_test_burst(ast, 3))
+		return false;
+	if (!mmc_test_single_2500(ast, 0))
+		return false;
+	return true;
+}
+
+static void ddr_init_common_2500(struct ast_private *ast)
+{
+	ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
+	ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
+	ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
+	ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
+	ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
+	ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
+	ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
+	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
+	ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
+	ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
+	ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
+	ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
+}
+
+static void ddr_phy_init_2500(struct ast_private *ast)
+{
+	u32 data, pass, timecnt;
+
+	pass = 0;
+	ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
+	while (!pass) {
+		for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
+			data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
+			if (!data)
+				break;
+		}
+		if (timecnt != TIMEOUT) {
+			data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
+			if (!data)
+				pass = 1;
+		}
+		if (!pass) {
+			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+			udelay(10); /* delay 10 us */
+			ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
+		}
+	}
+
+	ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
+}
+
+/*
+ * Check DRAM Size
+ * 1Gb : 0x80000000 ~ 0x87FFFFFF
+ * 2Gb : 0x80000000 ~ 0x8FFFFFFF
+ * 4Gb : 0x80000000 ~ 0x9FFFFFFF
+ * 8Gb : 0x80000000 ~ 0xBFFFFFFF
+ */
+static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
+{
+	u32 reg_04, reg_14;
+
+	reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
+	reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
+
+	ast_moutdwm(ast, 0xA0100000, 0x41424344);
+	ast_moutdwm(ast, 0x90100000, 0x35363738);
+	ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
+	ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
+
+	/* Check 8Gbit */
+	if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
+		reg_04 |= 0x03;
+		reg_14 |= (tRFC >> 24) & 0xFF;
+		/* Check 4Gbit */
+	} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
+		reg_04 |= 0x02;
+		reg_14 |= (tRFC >> 16) & 0xFF;
+		/* Check 2Gbit */
+	} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
+		reg_04 |= 0x01;
+		reg_14 |= (tRFC >> 8) & 0xFF;
+	} else {
+		reg_14 |= tRFC & 0xFF;
+	}
+	ast_moutdwm(ast, 0x1E6E0004, reg_04);
+	ast_moutdwm(ast, 0x1E6E0014, reg_14);
+}
+
+static void enable_cache_2500(struct ast_private *ast)
+{
+	u32 reg_04, data;
+
+	reg_04 = ast_mindwm(ast, 0x1E6E0004);
+	ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
+
+	do
+		data = ast_mindwm(ast, 0x1E6E0004);
+	while (!(data & 0x80000));
+	ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
+}
+
+static void set_mpll_2500(struct ast_private *ast)
+{
+	u32 addr, data, param;
+
+	/* Reset MMC */
+	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
+	ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
+	for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
+		ast_moutdwm(ast, addr, 0x0);
+		addr += 4;
+	}
+	ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
+
+	ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
+	data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
+	if (data) {
+		/* CLKIN = 25MHz */
+		param = 0x930023E0;
+		ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
+	} else {
+		/* CLKIN = 24MHz */
+		param = 0x93002400;
+	}
+	ast_moutdwm(ast, 0x1E6E2020, param);
+	udelay(100);
+}
+
+static void reset_mmc_2500(struct ast_private *ast)
+{
+	ast_moutdwm(ast, 0x1E78505C, 0x00000004);
+	ast_moutdwm(ast, 0x1E785044, 0x00000001);
+	ast_moutdwm(ast, 0x1E785048, 0x00004755);
+	ast_moutdwm(ast, 0x1E78504C, 0x00000013);
+	mdelay(100);
+	ast_moutdwm(ast, 0x1E785054, 0x00000077);
+	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
+}
+
+static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
+{
+
+	ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
+	ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
+	ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
+	ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
+	ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);	     /* MODEREG4/6 */
+	ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);	     /* MODEREG5 */
+	ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
+	ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);	     /* MODEREG1/3 */
+
+	/* DDR PHY Setting */
+	ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
+	ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
+	ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
+	ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
+	ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
+	ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
+	ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
+	ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
+	ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
+	ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
+	ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
+	ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
+	ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
+	ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
+
+	/* Controller Setting */
+	ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
+
+	/* Wait DDR PHY init done */
+	ddr_phy_init_2500(ast);
+
+	ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
+	ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
+	ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
+
+	check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
+	enable_cache_2500(ast);
+	ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
+	ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
+}
+
+static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
+{
+	u32 data, data2, pass, retrycnt;
+	u32 ddr_vref, phy_vref;
+	u32 min_ddr_vref = 0, min_phy_vref = 0;
+	u32 max_ddr_vref = 0, max_phy_vref = 0;
+
+	ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
+	ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
+	ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
+	ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
+	ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);	     /* MODEREG4/6 */
+	ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);	     /* MODEREG5 */
+	ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
+	ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);	     /* MODEREG1/3 */
+
+	/* DDR PHY Setting */
+	ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
+	ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
+	ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
+	ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
+	ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
+	ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
+	ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
+	ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
+	ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
+	ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
+	ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
+	ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
+	ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
+	ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
+	ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
+
+	/* Controller Setting */
+	ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
+
+	/* Train PHY Vref first */
+	pass = 0;
+
+	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
+		max_phy_vref = 0x0;
+		pass = 0;
+		ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
+		for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
+			ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
+			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+			ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
+			/* Fire DFI Init */
+			ddr_phy_init_2500(ast);
+			ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
+			if (cbr_test_2500(ast)) {
+				pass++;
+				data = ast_mindwm(ast, 0x1E6E03D0);
+				data2 = data >> 8;
+				data  = data & 0xff;
+				if (data > data2)
+					data = data2;
+				if (max_phy_vref < data) {
+					max_phy_vref = data;
+					min_phy_vref = phy_vref;
+				}
+			} else if (pass > 0)
+				break;
+		}
+	}
+	ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
+
+	/* Train DDR Vref next */
+	pass = 0;
+
+	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
+		min_ddr_vref = 0xFF;
+		max_ddr_vref = 0x0;
+		pass = 0;
+		for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
+			ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
+			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+			ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
+			/* Fire DFI Init */
+			ddr_phy_init_2500(ast);
+			ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
+			if (cbr_test_2500(ast)) {
+				pass++;
+				if (min_ddr_vref > ddr_vref)
+					min_ddr_vref = ddr_vref;
+				if (max_ddr_vref < ddr_vref)
+					max_ddr_vref = ddr_vref;
+			} else if (pass != 0)
+				break;
+		}
+	}
+
+	ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+	ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
+	ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
+
+	/* Wait DDR PHY init done */
+	ddr_phy_init_2500(ast);
+
+	ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
+	ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
+	ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
+
+	check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
+	enable_cache_2500(ast);
+	ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
+	ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
+}
+
+static bool ast_dram_init_2500(struct ast_private *ast)
+{
+	u32 data;
+	u32 max_tries = 5;
+
+	do {
+		if (max_tries-- == 0)
+			return false;
+		set_mpll_2500(ast);
+		reset_mmc_2500(ast);
+		ddr_init_common_2500(ast);
+
+		data = ast_mindwm(ast, 0x1E6E2070);
+		if (data & 0x01000000)
+			ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
+		else
+			ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
+	} while (!ddr_test_2500(ast));
+
+	ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
+
+	/* Patch code */
+	data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
+	ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
+
+	return true;
+}
+
+void ast_post_chip_2500(struct drm_device *dev)
+{
+	struct ast_private *ast = dev->dev_private;
+	u32 temp;
+	u8 reg;
+
+	reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
+	if ((reg & 0x80) == 0) {/* vga only */
+		/* Clear bus lock condition */
+		ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
+		ast_moutdwm(ast, 0x1e600084, 0x00010000);
+		ast_moutdwm(ast, 0x1e600088, 0x00000000);
+		ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
+		ast_write32(ast, 0xf004, 0x1e6e0000);
+		ast_write32(ast, 0xf000, 0x1);
+		ast_write32(ast, 0x12000, 0x1688a8a8);
+		while (ast_read32(ast, 0x12000) != 0x1)
+			;
+
+		ast_write32(ast, 0x10000, 0xfc600309);
+		while (ast_read32(ast, 0x10000) != 0x1)
+			;
+
+		/* Slow down CPU/AHB CLK in VGA only mode */
+		temp = ast_read32(ast, 0x12008);
+		temp |= 0x73;
+		ast_write32(ast, 0x12008, temp);
+
+		/* Reset USB port to patch USB unknown device issue */
+		ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
+		temp  = ast_mindwm(ast, 0x1e6e2094);
+		temp |= 0x00004000;
+		ast_moutdwm(ast, 0x1e6e2094, temp);
+		temp  = ast_mindwm(ast, 0x1e6e2070);
+		if (temp & 0x00800000) {
+			ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
+			mdelay(100);
+			ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
+		}
+
+		if (!ast_dram_init_2500(ast))
+			printk(BIOS_ERR, "AST: DRAM init failed !\n");
+
+		temp = ast_mindwm(ast, 0x1e6e2040);
+		ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
+	}
+
+	/* wait ready */
+	do {
+		reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
+	} while ((reg & 0x40) == 0);
 }
diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h
index 6c20f36..d665dd5 100644
--- a/src/drivers/aspeed/common/ast_tables.h
+++ b/src/drivers/aspeed/common/ast_tables.h
@@ -47,68 +47,99 @@
 #define SyncPN			(PVSync | NHSync)
 #define SyncNP			(NVSync | PHSync)
 #define SyncNN			(NVSync | NHSync)
+#define AST2500PreCatchCRT		0x00004000

/* DCLK Index */
-#define VCLK25_175		0x00
-#define VCLK28_322		0x01
-#define VCLK31_5		0x02
-#define VCLK36			0x03
-#define VCLK40			0x04
-#define VCLK49_5		0x05
-#define VCLK50			0x06
-#define VCLK56_25		0x07
-#define VCLK65			0x08
-#define VCLK75			0x09
-#define VCLK78_75		0x0A
-#define VCLK94_5		0x0B
-#define VCLK108			0x0C
-#define VCLK135			0x0D
-#define VCLK157_5		0x0E
-#define VCLK162			0x0F
-/* #define VCLK193_25		0x10 */
-#define VCLK154			0x10
-#define VCLK83_5		0x11
-#define VCLK106_5		0x12
-#define VCLK146_25		0x13
-#define VCLK148_5		0x14
-#define VCLK71			0x15
-#define VCLK88_75		0x16
-#define VCLK119			0x17
-#define VCLK85_5		0x18
-#define VCLK97_75		0x19
-#define VCLK118_25		0x1A
+#define VCLK25_175     		0x00
+#define VCLK28_322     		0x01
+#define VCLK31_5       		0x02
+#define VCLK36         		0x03
+#define VCLK40         		0x04
+#define VCLK49_5       		0x05
+#define VCLK50         		0x06
+#define VCLK56_25      		0x07
+#define VCLK65		 	0x08
+#define VCLK75	        	0x09
+#define VCLK78_75      		0x0A
+#define VCLK94_5       		0x0B
+#define VCLK108        		0x0C
+#define VCLK135        		0x0D
+#define VCLK157_5      		0x0E
+#define VCLK162        		0x0F
+/* #define VCLK193_25     		0x10 */
+#define VCLK154     		0x10
+#define VCLK83_5    		0x11
+#define VCLK106_5   		0x12
+#define VCLK146_25  		0x13
+#define VCLK148_5   		0x14
+#define VCLK71      		0x15
+#define VCLK88_75   		0x16
+#define VCLK119     		0x17
+#define VCLK85_5     		0x18
+#define VCLK97_75     		0x19
+#define VCLK118_25			0x1A

-static struct ast_vbios_dclk_info dclk_table[] = {
-	{0x2C, 0xE7, 0x03},		/* 00: VCLK25_175 */
-	{0x95, 0x62, 0x03},		/* 01: VCLK28_322 */
-	{0x67, 0x63, 0x01},		/* 02: VCLK31_5 */
-	{0x76, 0x63, 0x01},		/* 03: VCLK36 */
-	{0xEE, 0x67, 0x01},		/* 04: VCLK40 */
-	{0x82, 0x62, 0x01},		/* 05: VCLK49_5 */
-	{0xC6, 0x64, 0x01},		/* 06: VCLK50 */
-	{0x94, 0x62, 0x01},		/* 07: VCLK56_25 */
-	{0x80, 0x64, 0x00},		/* 08: VCLK65 */
-	{0x7B, 0x63, 0x00},		/* 09: VCLK75 */
-	{0x67, 0x62, 0x00},		/* 0A: VCLK78_75 */
-	{0x7C, 0x62, 0x00},		/* 0B: VCLK94_5 */
-	{0x8E, 0x62, 0x00},		/* 0C: VCLK108 */
-	{0x85, 0x24, 0x00},		/* 0D: VCLK135 */
-	{0x67, 0x22, 0x00},		/* 0E: VCLK157_5 */
-	{0x6A, 0x22, 0x00},		/* 0F: VCLK162 */
-	{0x4d, 0x4c, 0x80},		/* 10: VCLK154 */
-	{0xa7, 0x78, 0x80},		/* 11: VCLK83.5 */
-	{0x28, 0x49, 0x80},		/* 12: VCLK106.5 */
-	{0x37, 0x49, 0x80},		/* 13: VCLK146.25 */
-	{0x1f, 0x45, 0x80},		/* 14: VCLK148.5 */
-	{0x47, 0x6c, 0x80},		/* 15: VCLK71 */
-	{0x25, 0x65, 0x80},		/* 16: VCLK88.75 */
-	{0x77, 0x58, 0x80},		/* 17: VCLK119 */
-	{0x32, 0x67, 0x80},		/* 18: VCLK85_5 */
-	{0x6a, 0x6d, 0x80},		/* 19: VCLK97_75 */
-	{0x3b, 0x2c, 0x81},		/* 1A: VCLK118_25 */
+static const struct ast_vbios_dclk_info dclk_table[] = {
+	{0x2C, 0xE7, 0x03},			/* 00: VCLK25_175	*/
+	{0x95, 0x62, 0x03},			/* 01: VCLK28_322	*/
+	{0x67, 0x63, 0x01},			/* 02: VCLK31_5		*/
+	{0x76, 0x63, 0x01},			/* 03: VCLK36		*/
+	{0xEE, 0x67, 0x01},			/* 04: VCLK40		*/
+	{0x82, 0x62, 0x01},			/* 05: VCLK49_5		*/
+	{0xC6, 0x64, 0x01},			/* 06: VCLK50		*/
+	{0x94, 0x62, 0x01},			/* 07: VCLK56_25	*/
+	{0x80, 0x64, 0x00},			/* 08: VCLK65		*/
+	{0x7B, 0x63, 0x00},			/* 09: VCLK75		*/
+	{0x67, 0x62, 0x00},			/* 0A: VCLK78_75	*/
+	{0x7C, 0x62, 0x00},			/* 0B: VCLK94_5		*/
+	{0x8E, 0x62, 0x00},			/* 0C: VCLK108		*/
+	{0x85, 0x24, 0x00},			/* 0D: VCLK135		*/
+	{0x67, 0x22, 0x00},			/* 0E: VCLK157_5	*/
+	{0x6A, 0x22, 0x00},			/* 0F: VCLK162		*/
+	{0x4d, 0x4c, 0x80},			/* 10: VCLK154		*/
+	{0x68, 0x6f, 0x80},			/* 11: VCLK83.5		*/
+	{0x28, 0x49, 0x80},			/* 12: VCLK106.5	*/
+	{0x37, 0x49, 0x80},			/* 13: VCLK146.25	*/
+	{0x1f, 0x45, 0x80},			/* 14: VCLK148.5	*/
+	{0x47, 0x6c, 0x80},			/* 15: VCLK71		*/
+	{0x25, 0x65, 0x80},			/* 16: VCLK88.75	*/
+	{0x77, 0x58, 0x80},			/* 17: VCLK119		*/
+	{0x32, 0x67, 0x80},			/* 18: VCLK85_5		*/
+	{0x6a, 0x6d, 0x80},			/* 19: VCLK97_75	*/
+	{0x3b, 0x2c, 0x81},			/* 1A: VCLK118_25	*/
 };

-static struct ast_vbios_stdtable vbios_stdtable[] = {
+static const struct ast_vbios_dclk_info dclk_table_ast2500[] = {
+	{0x2C, 0xE7, 0x03},			/* 00: VCLK25_175	*/
+	{0x95, 0x62, 0x03},			/* 01: VCLK28_322	*/
+	{0x67, 0x63, 0x01},			/* 02: VCLK31_5		*/
+	{0x76, 0x63, 0x01},			/* 03: VCLK36		*/
+	{0xEE, 0x67, 0x01},			/* 04: VCLK40		*/
+	{0x82, 0x62, 0x01},			/* 05: VCLK49_5		*/
+	{0xC6, 0x64, 0x01},			/* 06: VCLK50		*/
+	{0x94, 0x62, 0x01},			/* 07: VCLK56_25	*/
+	{0x80, 0x64, 0x00},			/* 08: VCLK65		*/
+	{0x7B, 0x63, 0x00},			/* 09: VCLK75		*/
+	{0x67, 0x62, 0x00},			/* 0A: VCLK78_75	*/
+	{0x7C, 0x62, 0x00},			/* 0B: VCLK94_5		*/
+	{0x8E, 0x62, 0x00},			/* 0C: VCLK108		*/
+	{0x85, 0x24, 0x00},			/* 0D: VCLK135		*/
+	{0x67, 0x22, 0x00},			/* 0E: VCLK157_5	*/
+	{0x6A, 0x22, 0x00},			/* 0F: VCLK162		*/
+	{0x4d, 0x4c, 0x80},			/* 10: VCLK154		*/
+	{0x68, 0x6f, 0x80},			/* 11: VCLK83.5		*/
+	{0x28, 0x49, 0x80},			/* 12: VCLK106.5	*/
+	{0x37, 0x49, 0x80},			/* 13: VCLK146.25	*/
+	{0x1f, 0x45, 0x80},			/* 14: VCLK148.5	*/
+	{0x47, 0x6c, 0x80},			/* 15: VCLK71		*/
+	{0x25, 0x65, 0x80},			/* 16: VCLK88.75	*/
+	{0x58, 0x01, 0x42},			/* 17: VCLK119		*/
+	{0x32, 0x67, 0x80},			/* 18: VCLK85_5		*/
+	{0x6a, 0x6d, 0x80},			/* 19: VCLK97_75	*/
+	{0x44, 0x20, 0x43},			/* 1A: VCLK118_25	*/
+};
+
+static const struct ast_vbios_stdtable vbios_stdtable[] = {
    /* MD_2_3_400 */
    {
    	0x67,
@@ -181,7 +212,7 @@
    },
 };

-static struct ast_vbios_enhtable res_640x480[] = {
+static const struct ast_vbios_enhtable res_640x480[] = {
    { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175,	/* 60Hz */
      (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E },
    { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5,	/* 72Hz */
@@ -194,7 +225,7 @@
      (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E },
 };

-static struct ast_vbios_enhtable res_800x600[] = {
+static const struct ast_vbios_enhtable res_800x600[] = {
    {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36,	/* 56Hz */
     (SyncPP | Charx8Dot), 56, 1, 0x30 },
    {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40,	/* 60Hz */
@@ -210,7 +241,7 @@
 };

-static struct ast_vbios_enhtable res_1024x768[] = {
+static const struct ast_vbios_enhtable res_1024x768[] = {
    {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65,	/* 60Hz */
     (SyncNN | Charx8Dot), 60, 1, 0x31 },
    {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75,	/* 70Hz */
@@ -223,7 +254,7 @@
     (SyncPP | Charx8Dot), 0xFF, 4, 0x31 },
 };

-static struct ast_vbios_enhtable res_1280x1024[] = {
+static const struct ast_vbios_enhtable res_1280x1024[] = {
    {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108,	/* 60Hz */
     (SyncPP | Charx8Dot), 60, 1, 0x32 },
    {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135,	/* 75Hz */
@@ -234,7 +265,7 @@
     (SyncPP | Charx8Dot), 0xFF, 3, 0x32 },
 };

-static struct ast_vbios_enhtable res_1600x1200[] = {
+static const struct ast_vbios_enhtable res_1600x1200[] = {
    {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162,	/* 60Hz */
     (SyncPP | Charx8Dot), 60, 1, 0x33 },
    {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162,	/* end */
@@ -242,34 +273,39 @@
 };

/* 16:9 */
-static struct ast_vbios_enhtable res_1360x768[] = {
-	{1792, 1360, 64,112, 795,  768, 3, 6, VCLK85_5,	         /* 60Hz */
+static const struct ast_vbios_enhtable res_1360x768[] = {
+	{1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5,		/* 60Hz */
     (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 },
-	{1792, 1360, 64,112, 795,  768, 3, 6, VCLK85_5,	         /* end */
-	 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 },
+	{1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5,	         /* end */
+	 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+	  AST2500PreCatchCRT), 0xFF, 1, 0x39 },
 };

-static struct ast_vbios_enhtable res_1600x900[] = {
-	{1760, 1600, 48, 32, 926,  900, 3, 5, VCLK97_75,	/* 60Hz CVT RB */
-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A },
-	{2112, 1600, 88,168, 934,  900, 3, 5, VCLK118_25,	/* 60Hz CVT */
+static const struct ast_vbios_enhtable res_1600x900[] = {
+	{1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75,		/* 60Hz CVT RB */
+	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+	  AST2500PreCatchCRT), 60, 1, 0x3A },
+	{2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25,	/* 60Hz CVT */
     (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A },
-	{2112, 1600, 88,168, 934,  900, 3, 5, VCLK118_25,	/* 60Hz CVT */
+	{2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25,	/* 60Hz CVT */
     (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A },
 };

-static struct ast_vbios_enhtable res_1920x1080[] = {
+static const struct ast_vbios_enhtable res_1920x1080[] = {
    {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5,	/* 60Hz */
-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 },
+	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+	  AST2500PreCatchCRT), 60, 1, 0x38 },
    {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5,	/* 60Hz */
-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 },
+	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+	  AST2500PreCatchCRT), 0xFF, 1, 0x38 },
 };

/* 16:10 */
-static struct ast_vbios_enhtable res_1280x800[] = {
+static const struct ast_vbios_enhtable res_1280x800[] = {
    {1440, 1280, 48, 32,  823,  800, 3, 6, VCLK71,		/* 60Hz RB */
-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 },
+	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+	  AST2500PreCatchCRT), 60, 1, 0x35 },
    {1680, 1280, 72,128,  831,  800, 3, 6, VCLK83_5,	/* 60Hz */
     (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 },
    {1680, 1280, 72,128,  831,  800, 3, 6, VCLK83_5,	/* 60Hz */
@@ -277,29 +313,33 @@

};

-static struct ast_vbios_enhtable res_1440x900[] = {
+static const struct ast_vbios_enhtable res_1440x900[] = {
    {1600, 1440, 48, 32,  926,  900, 3, 6, VCLK88_75,	/* 60Hz RB */
-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 },
+	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+	  AST2500PreCatchCRT), 60, 1, 0x36 },
    {1904, 1440, 80,152,  934,  900, 3, 6, VCLK106_5,	/* 60Hz */
     (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 },
    {1904, 1440, 80,152,  934,  900, 3, 6, VCLK106_5,	/* 60Hz */
     (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 },
 };

-static struct ast_vbios_enhtable res_1680x1050[] = {
+static const struct ast_vbios_enhtable res_1680x1050[] = {
    {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119,		/* 60Hz RB */
-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 },
+	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+	  AST2500PreCatchCRT), 60, 1, 0x37 },
    {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25,	/* 60Hz */
     (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 },
    {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25,	/* 60Hz */
     (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 },
 };

-static struct ast_vbios_enhtable res_1920x1200[] = {
+static const struct ast_vbios_enhtable res_1920x1200[] = {
    {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,		/* 60Hz RB*/
-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 },
-	{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,	/* 60Hz RB */
-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 },
+	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+	  AST2500PreCatchCRT), 60, 1, 0x34 },
+	{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,		/* 60Hz RB */
+	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+	  AST2500PreCatchCRT), 0xFF, 1, 0x34 },
 };

#endif

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: [WIP]drivers/aspeed: Add AST2500 support
......................................................................

Patch Set 1:

(27 comments)

https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
File src/drivers/aspeed/common/ast_tables.h:

https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 53: #define VCLK25_175     		0x00
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 54: #define VCLK28_322     		0x01
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 55: #define VCLK31_5       		0x02
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 56: #define VCLK36         		0x03
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 57: #define VCLK40         		0x04
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 58: #define VCLK49_5       		0x05
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 59: #define VCLK50         		0x06
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 60: #define VCLK56_25      		0x07
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 61: #define VCLK65		 	0x08
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 62: #define VCLK75	        	0x09
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 63: #define VCLK78_75      		0x0A
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 64: #define VCLK94_5       		0x0B
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 65: #define VCLK108        		0x0C
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 66: #define VCLK135        		0x0D
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 67: #define VCLK157_5      		0x0E
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 68: #define VCLK162        		0x0F
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 69: /* #define VCLK193_25     		0x10 */
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 70: #define VCLK154     		0x10
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 71: #define VCLK83_5    		0x11
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 72: #define VCLK106_5   		0x12
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 73: #define VCLK146_25  		0x13
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 74: #define VCLK148_5   		0x14
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 75: #define VCLK71      		0x15
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 76: #define VCLK88_75   		0x16
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 77: #define VCLK119     		0x17
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 78: #define VCLK85_5     		0x18
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https://review.coreboot.org/c/coreboot/+/34793/1/src/drivers/aspeed/common/a... 
PS1, Line 79: #define VCLK97_75     		0x19
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[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: [WIP]drivers/aspeed: Add AST2500 support
......................................................................

Patch Set 2:

(27 comments)

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
File src/drivers/aspeed/common/ast_tables.h:

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 53: #define VCLK25_175     		0x00
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 54: #define VCLK28_322     		0x01
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 55: #define VCLK31_5       		0x02
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 56: #define VCLK36         		0x03
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 57: #define VCLK40         		0x04
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 58: #define VCLK49_5       		0x05
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 59: #define VCLK50         		0x06
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 60: #define VCLK56_25      		0x07
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 61: #define VCLK65		 	0x08
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 62: #define VCLK75	        	0x09
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 63: #define VCLK78_75      		0x0A
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 64: #define VCLK94_5       		0x0B
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 65: #define VCLK108        		0x0C
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 66: #define VCLK135        		0x0D
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 67: #define VCLK157_5      		0x0E
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 68: #define VCLK162        		0x0F
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 69: /* #define VCLK193_25     		0x10 */
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 70: #define VCLK154     		0x10
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 71: #define VCLK83_5    		0x11
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 72: #define VCLK106_5   		0x12
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 73: #define VCLK146_25  		0x13
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 74: #define VCLK148_5   		0x14
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 75: #define VCLK71      		0x15
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 76: #define VCLK88_75   		0x16
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 77: #define VCLK119     		0x17
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 78: #define VCLK85_5     		0x18
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https://review.coreboot.org/c/coreboot/+/34793/2/src/drivers/aspeed/common/a... 
PS2, Line 79: #define VCLK97_75     		0x19
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[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: [WIP]drivers/aspeed: Add AST2500 support
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34793/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34793/2//COMMIT_MSG@14 
PS2, Line 14: GNU/Linux kernel
What commit/release?

Change in coreboot[master]: drivers/aspeed: Add AST2500 support

[Patrick Rudolph (Code Review)]

Hello Christian Walter, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34793

to look at the new patch set (#5).

Change subject: drivers/aspeed: Add AST2500 support
......................................................................

drivers/aspeed: Add AST2500 support

Copy code from GNU/Linux kernel to coreboot to add AST2500 support.

Tested on Supermicro X11SCH on AST2500.
Code for AST2400 still works.

Change-Id: I25bd34dd52a0acd3e04fc5818e011215ef907fad
Signed-off-by: Patrick Rudolph 
---
M src/drivers/aspeed/common/ast_dp501.c
M src/drivers/aspeed/common/ast_dram_tables.h
M src/drivers/aspeed/common/ast_drv.h
M src/drivers/aspeed/common/ast_main.c
M src/drivers/aspeed/common/ast_post.c
5 files changed, 553 insertions(+), 84 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/34793/5

Change in coreboot[master]: drivers/aspeed: Add AST2500 support

[Christian Walter (Code Review)]

Christian Walter has uploaded a new patch set (#6) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: drivers/aspeed: Add AST2500 support
......................................................................

drivers/aspeed: Add AST2500 support

Untested on AST2500.
Code for AST2400 still works.

Copy code from GNU/Linux kernel to coreboot to add AST2500 support.

Change-Id: I25bd34dd52a0acd3e04fc5818e011215ef907fad
Signed-off-by: Patrick Rudolph 
---
M src/drivers/aspeed/common/ast_dp501.c
M src/drivers/aspeed/common/ast_dram_tables.h
M src/drivers/aspeed/common/ast_drv.h
M src/drivers/aspeed/common/ast_main.c
M src/drivers/aspeed/common/ast_post.c
5 files changed, 553 insertions(+), 84 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/34793/6

Change in coreboot[master]: drivers/aspeed: Add AST2500 support

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: drivers/aspeed: Add AST2500 support
......................................................................

Patch Set 9: Code-Review+2

Change in coreboot[master]: drivers/aspeed: Add AST2500 support

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: drivers/aspeed: Add AST2500 support
......................................................................

Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34793/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34793/2//COMMIT_MSG@14 
PS2, Line 14: GNU/Linux kernel
> What commit/release?

Linux 5.2

Change in coreboot[master]: drivers/aspeed: Add AST2500 support

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded a new patch set (#11) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: drivers/aspeed: Add AST2500 support
......................................................................

drivers/aspeed: Add AST2500 support

Tested on AST2500.
Code for AST2400 still works.

Copy code from GNU/Linux kernel to coreboot to add AST2500 support.

Change-Id: I25bd34dd52a0acd3e04fc5818e011215ef907fad
Signed-off-by: Patrick Rudolph 
---
M src/drivers/aspeed/common/ast_dp501.c
M src/drivers/aspeed/common/ast_dram_tables.h
M src/drivers/aspeed/common/ast_drv.h
M src/drivers/aspeed/common/ast_main.c
M src/drivers/aspeed/common/ast_post.c
5 files changed, 553 insertions(+), 84 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/34793/11

Change in coreboot[master]: drivers/aspeed: Add AST2500 support

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: drivers/aspeed: Add AST2500 support
......................................................................

Patch Set 11: Code-Review+2

Change in coreboot[master]: drivers/aspeed: Add AST2500 support

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34793 )

Change subject: drivers/aspeed: Add AST2500 support
......................................................................

drivers/aspeed: Add AST2500 support

Tested on AST2500.
Code for AST2400 still works.

Copy code from GNU/Linux kernel to coreboot to add AST2500 support.

Change-Id: I25bd34dd52a0acd3e04fc5818e011215ef907fad
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34793
Tested-by: build bot (Jenkins) 
Reviewed-by: Philipp Deppenwiese 
---
M src/drivers/aspeed/common/ast_dp501.c
M src/drivers/aspeed/common/ast_dram_tables.h
M src/drivers/aspeed/common/ast_drv.h
M src/drivers/aspeed/common/ast_main.c
M src/drivers/aspeed/common/ast_post.c
5 files changed, 553 insertions(+), 84 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Philipp Deppenwiese: Looks good to me, approved

diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c
index 99b0875..2954744 100644
--- a/src/drivers/aspeed/common/ast_dp501.c
+++ b/src/drivers/aspeed/common/ast_dp501.c
@@ -147,7 +147,7 @@
    return false;
 }

-bool ast_launch_m68k(struct drm_device *dev)
+static bool ast_launch_m68k(struct drm_device *dev)
 {
    struct ast_private *ast = dev->dev_private;
    u32 i, data, len = 0;
@@ -161,7 +161,10 @@
    	if (ast->dp501_fw_addr) {
    		fw_addr = ast->dp501_fw_addr;
    		len = 32*1024;
-		} else if (ast->dp501_fw) {
+		} else {
+			if (!ast->dp501_fw)
+				return false;
+
    		fw_addr = (u8 *)ast->dp501_fw->data;
    		len = ast->dp501_fw->size;
    	}
@@ -226,11 +229,7 @@

/* Read Link Capability */
    offset  = 0xf014;
-	data = ast_mindwm(ast, boot_address + offset);
-	linkcap[0] = (data & 0xff000000) >> 24;
-	linkcap[1] = (data & 0x00ff0000) >> 16;
-	linkcap[2] = (data & 0x0000ff00) >> 8;
-	linkcap[3] = (data & 0x000000ff);
+	*(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
    if (linkcap[2] == 0) {
    	linkrate = linkcap[0];
    	linklanes = linkcap[1];
diff --git a/src/drivers/aspeed/common/ast_dram_tables.h b/src/drivers/aspeed/common/ast_dram_tables.h
index 39495d3..69894fc 100644
--- a/src/drivers/aspeed/common/ast_dram_tables.h
+++ b/src/drivers/aspeed/common/ast_dram_tables.h
@@ -159,4 +159,66 @@
    { 0xffff, 0xffffffff },
 };

+/*
+ * AST2500 DRAM settings modules
+ */
+#define REGTBL_NUM		17
+#define REGIDX_010		0
+#define REGIDX_014		1
+#define REGIDX_018		2
+#define REGIDX_020		3
+#define REGIDX_024		4
+#define REGIDX_02C		5
+#define REGIDX_030		6
+#define REGIDX_214		7
+#define REGIDX_2E0		8
+#define REGIDX_2E4		9
+#define REGIDX_2E8		10
+#define REGIDX_2EC		11
+#define REGIDX_2F0		12
+#define REGIDX_2F4		13
+#define REGIDX_2F8		14
+#define REGIDX_RFC		15
+#define REGIDX_PLL		16
+
+static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
+	0x64604D38,			/* 0x010 */
+	0x29690599,			/* 0x014 */
+	0x00000300,			/* 0x018 */
+	0x00000000,			/* 0x020 */
+	0x00000000,			/* 0x024 */
+	0x02181E70,			/* 0x02C */
+	0x00000040,			/* 0x030 */
+	0x00000024,			/* 0x214 */
+	0x02001300,			/* 0x2E0 */
+	0x0E0000A0,			/* 0x2E4 */
+	0x000E001B,			/* 0x2E8 */
+	0x35B8C105,			/* 0x2EC */
+	0x08090408,			/* 0x2F0 */
+	0x9B000800,			/* 0x2F4 */
+	0x0E400A00,			/* 0x2F8 */
+	0x9971452F,			/* tRFC  */
+	0x000071C1			/* PLL   */
+	};
+
+	static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
+	0x63604E37,			/* 0x010 */
+	0xE97AFA99,			/* 0x014 */
+	0x00019000,			/* 0x018 */
+	0x08000000,			/* 0x020 */
+	0x00000400,			/* 0x024 */
+	0x00000410,			/* 0x02C */
+	0x00000101,			/* 0x030 */
+	0x00000024,			/* 0x214 */
+	0x03002900,			/* 0x2E0 */
+	0x0E0000A0,			/* 0x2E4 */
+	0x000E001C,			/* 0x2E8 */
+	0x35B8C106,			/* 0x2EC */
+	0x08080607,			/* 0x2F0 */
+	0x9B000900,			/* 0x2F4 */
+	0x0E400A00,			/* 0x2F8 */
+	0x99714545,			/* tRFC  */
+	0x000071C1			/* PLL   */
+	};
+
 #endif
diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h
index 39f4943..1c44026 100644
--- a/src/drivers/aspeed/common/ast_drv.h
+++ b/src/drivers/aspeed/common/ast_drv.h
@@ -63,6 +63,7 @@
 #define AST_DRAM_1Gx32   3
 #define AST_DRAM_2Gx16   6
 #define AST_DRAM_4Gx16   7
+#define AST_DRAM_8Gx16   8

struct ast_fbdev;

@@ -311,13 +312,12 @@
 u32 ast_mindwm(struct ast_private *ast, u32 r);
 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
 /* ast dp501 */
-int ast_load_dp501_microcode(struct drm_device *dev);
 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
-bool ast_launch_m68k(struct drm_device *dev);
 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
 u8 ast_get_dp501_max_clk(struct drm_device *dev);
 void ast_init_3rdtx(struct drm_device *dev);
+void ast_release_firmware(struct drm_device *dev);

/* ast mode */
 int ast_crtc_mode_set(struct drm_crtc *crtc,
diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c
index f9fb5e2..0a26a9c 100644
--- a/src/drivers/aspeed/common/ast_main.c
+++ b/src/drivers/aspeed/common/ast_main.c
@@ -75,8 +75,10 @@
    } else {
    	pci_read_config_dword(ast->dev->pdev, 0x08, &data);
    	uint8_t revision = data & 0xff;
-
-		if (revision >= 0x30) {
+		if (revision >= 0x40) {
+			ast->chip = AST2500;
+			DRM_INFO("AST 2500 detected\n");
+		} else if (revision >= 0x30) {
    		ast->chip = AST2400;
    		DRM_INFO("AST 2400 detected\n");
    	} else if (revision >= 0x20) {
@@ -151,6 +153,8 @@
    			ast->support_wide_screen = true;
    		if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
    			ast->support_wide_screen = true;
+			if (ast->chip == AST2500 && data == 0x100) /* ast2510 */
+				ast->support_wide_screen = true;
    	}
    	break;
    }
@@ -241,7 +245,23 @@
    else
    	ast->dram_bus_width = 32;

-	if (ast->chip == AST2300 || ast->chip == AST2400) {
+	if (ast->chip == AST2500) {
+		switch (data & 0x03) {
+		case 0:
+			ast->dram_type = AST_DRAM_1Gx16;
+			break;
+		default:
+		case 1:
+			ast->dram_type = AST_DRAM_2Gx16;
+			break;
+		case 2:
+			ast->dram_type = AST_DRAM_4Gx16;
+			break;
+		case 3:
+			ast->dram_type = AST_DRAM_8Gx16;
+			break;
+		}
+	} else if (ast->chip == AST2300 || ast->chip == AST2400) {
    	switch (data & 0x03) {
    	case 0:
    		ast->dram_type = AST_DRAM_512Mx16;
diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c
index d14082e..d4ee8b4 100644
--- a/src/drivers/aspeed/common/ast_post.c
+++ b/src/drivers/aspeed/common/ast_post.c
@@ -33,7 +33,8 @@
 #include "ast_drv.h"
 #include "ast_dram_tables.h"

-static void ast_init_dram_2300(struct drm_device *dev);
+static void ast_post_chip_2300(struct drm_device *dev);
+static void ast_post_chip_2500(struct drm_device *dev);

void ast_enable_vga(struct drm_device *dev)
 {
@@ -60,13 +61,9 @@
    	/* TODO 1180 */
    } else {
    	ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
-		if (ch) {
-			ast_open_key(ast);
-			ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff);
-			return ch & 0x04;
-		}
+		return !!(ch & 0x01);
    }
-	return 0;
+	return false;
 }

static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
@@ -85,10 +82,11 @@
    uint8_t revision = data & 0xff;

/* reset scratch */
-	for (i = 0x81; i <= 0x8f; i++)
+	for (i = 0x81; i <= 0x9f; i++)
    	ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);

-	if (ast->chip == AST2300 || ast->chip == AST2400) {
+	if (ast->chip == AST2300 || ast->chip == AST2400 ||
+	    ast->chip == AST2500) {
    	if (revision >= 0x20)
    		ext_reg_info = extreginfo_ast2300;
    	else
@@ -112,7 +110,8 @@

/* Enable RAMDAC for A1 */
    reg = 0x04;
-	if (ast->chip == AST2300 || ast->chip == AST2400)
+	if (ast->chip == AST2300 || ast->chip == AST2400 ||
+	    ast->chip == AST2500)
    	reg |= 0x20;
    ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
 }
@@ -393,12 +392,14 @@
    pci_write_config_dword(ast->dev->pdev, 0x04, reg);

ast_enable_vga(dev);
-	ast_enable_mmio(dev);
    ast_open_key(ast);
+	ast_enable_mmio(dev);
    ast_set_def_ext_reg(dev);

-	if (ast->chip == AST2300 || ast->chip == AST2400)
-		ast_init_dram_2300(dev);
+	if (ast->chip == AST2500)
+		ast_post_chip_2500(dev);
+	else if (ast->chip == AST2300 || ast->chip == AST2400)
+		ast_post_chip_2300(dev);
    else
    	ast_init_dram_reg(dev);

@@ -458,87 +459,72 @@
    0x7C61D253
 };

-static int mmc_test_burst(struct ast_private *ast, u32 datagen)
+static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
 {
    u32 data, timeout;

ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
-	timeout = 0;
-	do {
-		data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
-		if (data & 0x2000) {
-			return 0;
-		}
-		if (++timeout > TIMEOUT) {
-			ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-			return 0;
-		}
-	} while (!data);
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	return 1;
-}
-
-static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
-{
-	u32 data, timeout;
-
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
-	timeout = 0;
-	do {
-		data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
-		if (++timeout > TIMEOUT) {
-			ast_moutdwm(ast, 0x1e6e0070, 0x0);
-			return -1;
-		}
-	} while (!data);
-	data = ast_mindwm(ast, 0x1e6e0078);
-	data = (data | (data >> 16)) & 0xffff;
-	ast_moutdwm(ast, 0x1e6e0070, 0x0);
-	return data;
-}
-
-static int mmc_test_single(struct ast_private *ast, u32 datagen)
-{
-	u32 data, timeout;
-
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
+	ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
    timeout = 0;
    do {
    	data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
    	if (data & 0x2000)
-			return 0;
+			return false;
    	if (++timeout > TIMEOUT) {
-			ast_moutdwm(ast, 0x1e6e0070, 0x0);
-			return 0;
+			ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
+			return false;
    	}
    } while (!data);
    ast_moutdwm(ast, 0x1e6e0070, 0x0);
-	return 1;
+	return true;
 }

-static int mmc_test_single2(struct ast_private *ast, u32 datagen)
+static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
 {
    u32 data, timeout;

ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-	ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
+	ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
    timeout = 0;
    do {
    	data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
    	if (++timeout > TIMEOUT) {
    		ast_moutdwm(ast, 0x1e6e0070, 0x0);
-			return -1;
+			return 0xffffffff;
    	}
    } while (!data);
    data = ast_mindwm(ast, 0x1e6e0078);
    data = (data | (data >> 16)) & 0xffff;
-	ast_moutdwm(ast, 0x1e6e0070, 0x0);
+	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
    return data;
 }

+
+static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test(ast, datagen, 0xc1);
+}
+
+static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test2(ast, datagen, 0x41);
+}
+
+static bool mmc_test_single(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test(ast, datagen, 0xc5);
+}
+
+static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test2(ast, datagen, 0x05);
+}
+
+static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
+{
+	return mmc_test(ast, datagen, 0x85);
+}
+
 static int cbr_test(struct ast_private *ast)
 {
    u32 data;
@@ -614,16 +600,16 @@
    return data2;
 }

-static u32 cbr_test3(struct ast_private *ast)
+static bool cbr_test3(struct ast_private *ast)
 {
    if (!mmc_test_burst(ast, 0))
-		return 0;
+		return false;
    if (!mmc_test_single(ast, 0))
-		return 0;
-	return 1;
+		return false;
+	return true;
 }

-static u32 cbr_scan3(struct ast_private *ast)
+static bool cbr_scan3(struct ast_private *ast)
 {
    u32 patcnt, loop;

@@ -634,9 +620,9 @@
    			break;
    	}
    	if (loop == 2)
-			return 0;
+			return false;
    }
-	return 1;
+	return true;
 }

static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
@@ -1660,7 +1646,7 @@

}

-static void ast_init_dram_2300(struct drm_device *dev)
+static void ast_post_chip_2300(struct drm_device *dev)
 {
    struct ast_private *ast = dev->dev_private;
    struct ast2300_dram_param param;
@@ -1753,3 +1739,405 @@
    if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT)
    	dev_err(dev->pdev, "Timeout while waiting for register\n");
 }
+
+static bool cbr_test_2500(struct ast_private *ast)
+{
+	ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
+	ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
+	if (!mmc_test_burst(ast, 0))
+		return false;
+	if (!mmc_test_single_2500(ast, 0))
+		return false;
+	return true;
+}
+
+static bool ddr_test_2500(struct ast_private *ast)
+{
+	ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
+	ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
+	if (!mmc_test_burst(ast, 0))
+		return false;
+	if (!mmc_test_burst(ast, 1))
+		return false;
+	if (!mmc_test_burst(ast, 2))
+		return false;
+	if (!mmc_test_burst(ast, 3))
+		return false;
+	if (!mmc_test_single_2500(ast, 0))
+		return false;
+	return true;
+}
+
+static void ddr_init_common_2500(struct ast_private *ast)
+{
+	ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
+	ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
+	ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
+	ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
+	ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
+	ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
+	ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
+	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
+	ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
+	ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
+	ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
+	ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
+}
+
+static void ddr_phy_init_2500(struct ast_private *ast)
+{
+	u32 data, pass, timecnt;
+
+	pass = 0;
+	ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
+	while (!pass) {
+		for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
+			data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
+			if (!data)
+				break;
+		}
+		if (timecnt != TIMEOUT) {
+			data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
+			if (!data)
+				pass = 1;
+		}
+		if (!pass) {
+			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+			udelay(10); /* delay 10 us */
+			ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
+		}
+	}
+
+	ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
+}
+
+/*
+ * Check DRAM Size
+ * 1Gb : 0x80000000 ~ 0x87FFFFFF
+ * 2Gb : 0x80000000 ~ 0x8FFFFFFF
+ * 4Gb : 0x80000000 ~ 0x9FFFFFFF
+ * 8Gb : 0x80000000 ~ 0xBFFFFFFF
+ */
+static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
+{
+	u32 reg_04, reg_14;
+
+	reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
+	reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
+
+	ast_moutdwm(ast, 0xA0100000, 0x41424344);
+	ast_moutdwm(ast, 0x90100000, 0x35363738);
+	ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
+	ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
+
+	/* Check 8Gbit */
+	if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
+		reg_04 |= 0x03;
+		reg_14 |= (tRFC >> 24) & 0xFF;
+		/* Check 4Gbit */
+	} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
+		reg_04 |= 0x02;
+		reg_14 |= (tRFC >> 16) & 0xFF;
+		/* Check 2Gbit */
+	} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
+		reg_04 |= 0x01;
+		reg_14 |= (tRFC >> 8) & 0xFF;
+	} else {
+		reg_14 |= tRFC & 0xFF;
+	}
+	ast_moutdwm(ast, 0x1E6E0004, reg_04);
+	ast_moutdwm(ast, 0x1E6E0014, reg_14);
+}
+
+static void enable_cache_2500(struct ast_private *ast)
+{
+	u32 reg_04, data;
+
+	reg_04 = ast_mindwm(ast, 0x1E6E0004);
+	ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
+
+	do
+		data = ast_mindwm(ast, 0x1E6E0004);
+	while (!(data & 0x80000));
+	ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
+}
+
+static void set_mpll_2500(struct ast_private *ast)
+{
+	u32 addr, data, param;
+
+	/* Reset MMC */
+	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
+	ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
+	for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
+		ast_moutdwm(ast, addr, 0x0);
+		addr += 4;
+	}
+	ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
+
+	ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
+	data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
+	if (data) {
+		/* CLKIN = 25MHz */
+		param = 0x930023E0;
+		ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
+	} else {
+		/* CLKIN = 24MHz */
+		param = 0x93002400;
+	}
+	ast_moutdwm(ast, 0x1E6E2020, param);
+	udelay(100);
+}
+
+static void reset_mmc_2500(struct ast_private *ast)
+{
+	ast_moutdwm(ast, 0x1E78505C, 0x00000004);
+	ast_moutdwm(ast, 0x1E785044, 0x00000001);
+	ast_moutdwm(ast, 0x1E785048, 0x00004755);
+	ast_moutdwm(ast, 0x1E78504C, 0x00000013);
+	mdelay(100);
+	ast_moutdwm(ast, 0x1E785054, 0x00000077);
+	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
+}
+
+static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
+{
+
+	ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
+	ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
+	ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
+	ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
+	ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);	     /* MODEREG4/6 */
+	ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);	     /* MODEREG5 */
+	ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
+	ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);	     /* MODEREG1/3 */
+
+	/* DDR PHY Setting */
+	ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
+	ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
+	ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
+	ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
+	ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
+	ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
+	ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
+	ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
+	ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
+	ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
+	ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
+	ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
+	ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
+	ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
+
+	/* Controller Setting */
+	ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
+
+	/* Wait DDR PHY init done */
+	ddr_phy_init_2500(ast);
+
+	ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
+	ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
+	ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
+
+	check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
+	enable_cache_2500(ast);
+	ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
+	ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
+}
+
+static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
+{
+	u32 data, data2, pass, retrycnt;
+	u32 ddr_vref, phy_vref;
+	u32 min_ddr_vref = 0, min_phy_vref = 0;
+	u32 max_ddr_vref = 0, max_phy_vref = 0;
+
+	ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
+	ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
+	ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
+	ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
+	ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);	     /* MODEREG4/6 */
+	ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);	     /* MODEREG5 */
+	ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
+	ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);	     /* MODEREG1/3 */
+
+	/* DDR PHY Setting */
+	ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
+	ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
+	ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
+	ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
+	ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
+	ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
+	ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
+	ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
+	ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
+	ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
+	ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
+	ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
+	ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
+	ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
+	ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
+
+	/* Controller Setting */
+	ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
+
+	/* Train PHY Vref first */
+	pass = 0;
+
+	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
+		max_phy_vref = 0x0;
+		pass = 0;
+		ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
+		for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
+			ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
+			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+			ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
+			/* Fire DFI Init */
+			ddr_phy_init_2500(ast);
+			ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
+			if (cbr_test_2500(ast)) {
+				pass++;
+				data = ast_mindwm(ast, 0x1E6E03D0);
+				data2 = data >> 8;
+				data  = data & 0xff;
+				if (data > data2)
+					data = data2;
+				if (max_phy_vref < data) {
+					max_phy_vref = data;
+					min_phy_vref = phy_vref;
+				}
+			} else if (pass > 0)
+				break;
+		}
+	}
+	ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
+
+	/* Train DDR Vref next */
+	pass = 0;
+
+	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
+		min_ddr_vref = 0xFF;
+		max_ddr_vref = 0x0;
+		pass = 0;
+		for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
+			ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
+			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+			ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
+			/* Fire DFI Init */
+			ddr_phy_init_2500(ast);
+			ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
+			if (cbr_test_2500(ast)) {
+				pass++;
+				if (min_ddr_vref > ddr_vref)
+					min_ddr_vref = ddr_vref;
+				if (max_ddr_vref < ddr_vref)
+					max_ddr_vref = ddr_vref;
+			} else if (pass != 0)
+				break;
+		}
+	}
+
+	ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
+	ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+	ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
+	ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
+
+	/* Wait DDR PHY init done */
+	ddr_phy_init_2500(ast);
+
+	ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
+	ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
+	ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
+
+	check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
+	enable_cache_2500(ast);
+	ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
+	ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
+}
+
+static bool ast_dram_init_2500(struct ast_private *ast)
+{
+	u32 data;
+	u32 max_tries = 5;
+
+	do {
+		if (max_tries-- == 0)
+			return false;
+		set_mpll_2500(ast);
+		reset_mmc_2500(ast);
+		ddr_init_common_2500(ast);
+
+		data = ast_mindwm(ast, 0x1E6E2070);
+		if (data & 0x01000000)
+			ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
+		else
+			ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
+	} while (!ddr_test_2500(ast));
+
+	ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
+
+	/* Patch code */
+	data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
+	ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
+
+	return true;
+}
+
+void ast_post_chip_2500(struct drm_device *dev)
+{
+	struct ast_private *ast = dev->dev_private;
+	u32 temp;
+	u8 reg;
+
+	reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
+	if ((reg & 0x80) == 0) {/* vga only */
+		/* Clear bus lock condition */
+		ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
+		ast_moutdwm(ast, 0x1e600084, 0x00010000);
+		ast_moutdwm(ast, 0x1e600088, 0x00000000);
+		ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
+		ast_write32(ast, 0xf004, 0x1e6e0000);
+		ast_write32(ast, 0xf000, 0x1);
+		ast_write32(ast, 0x12000, 0x1688a8a8);
+		while (ast_read32(ast, 0x12000) != 0x1)
+			;
+
+		ast_write32(ast, 0x10000, 0xfc600309);
+		while (ast_read32(ast, 0x10000) != 0x1)
+			;
+
+		/* Slow down CPU/AHB CLK in VGA only mode */
+		temp = ast_read32(ast, 0x12008);
+		temp |= 0x73;
+		ast_write32(ast, 0x12008, temp);
+
+		/* Reset USB port to patch USB unknown device issue */
+		ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
+		temp  = ast_mindwm(ast, 0x1e6e2094);
+		temp |= 0x00004000;
+		ast_moutdwm(ast, 0x1e6e2094, temp);
+		temp  = ast_mindwm(ast, 0x1e6e2070);
+		if (temp & 0x00800000) {
+			ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
+			mdelay(100);
+			ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
+		}
+
+		if (!ast_dram_init_2500(ast))
+			printk(BIOS_ERR, "AST: DRAM init failed !\n");
+
+		temp = ast_mindwm(ast, 0x1e6e2040);
+		ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
+	}
+
+	/* wait ready */
+	do {
+		reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
+	} while ((reg & 0x40) == 0);
+}