Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 )
Change subject: drivers/fsp2_0: drop support for FSP-T ......................................................................
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> Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > Patch Set 4: Code-Review-1 > > > > > > > > > > > > > > FSP-T already set as optional. Some of our customers are using FSP-T, it has to be there. > > > > > > > > > > > > Could you please state why? What does FSP-T do that coreboot cannot? > > > > > > > > > > I understand the concern Arthur. > > > > > > > > > > There are some customer who still like to make use of FSP-T due to various reason. > > > > > > > > > > 1. native CAR implementation majorly focusing on NEM enhance > > > > > 2. Some customers like to use FSP-T with intel boot guard solution, where else native CAR what we implemented is not applicable with bootguard > > > > > > > > Can you give more details on that NEM part, please? > > > > here you go > > https://software.intel.com/en-us/articles/introduction-to-cache-allocation-t... > > > > > > On 2: is there any chance, Intel can release more details here so we can (maybe) add support for it? > > So this is supported by fsp-t but not cb native, yet? Is it just writing some registers/msrs or is more needed to get CAT working?
Ah, looks like just MSRs. But what exactly does FSP-T have to do with that?
let me explain it little better. FSP-T doesn't support CAT where Coreboot is supporting CAT. Current CAT implementation won't work with bootguard enable. As all FSP-T consumers are also willing to use bootguard solution hence they are not keen to use native CB CAR logic. And for current coreboot usage (frok google) doesn't bother to use bootguard hence we are good with CAT/NEM enhanced implementation.
So it's just a matter of using NEM instead of NEM enhanced? coreboot has that too.
sorry if it sounds otherwise. NEM enhance = CAT and both can't work with bootguard enable
No I meant that coreboot has code to do CAR without NEM enhance, but with just NEM. Would that satisfy the bootguard requirements?
NEM mode won't work with latest coreboot RO and RW design where romstage in RW. We will see hang during verstage if you not selecting NEM enhance and just select NEM mode.
But that is something not specific to coreboot NEM implementation but NEM in general so also the implementation in FSP-T? It's weird that it would hang after verstage. The CAR itself is not evicted and if cachelines are full the romstage in RW just gets XIP uncached in that case. Another option is not cache the whole ROM, run verstage and setup XIP cache for the romstage. See how CB:35994 does that.
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Arthur Heymans (Code Review)