Change in coreboot[master]: soc/intel/skylake: pch rp groups

[Felix Singer (Code Review)]

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52627 )

Change subject: soc/intel/skylake: pch rp groups
......................................................................

soc/intel/skylake: pch rp groups

Change-Id: I0d5155356bd302ef938c76eb60688276fec67502
Signed-off-by: Felix Singer 
---
M src/soc/intel/skylake/chip.c
1 file changed, 8 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/52627/1

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index d4e8341..dc6f2ad 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -32,13 +32,8 @@

#include "chip.h"

-static const struct pcie_rp_group pch_lp_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4 },
-	{ 0 }
-};
-
-static const struct pcie_rp_group pch_h_rp_groups[] = {
+static const struct pcie_rp_group pch_rp_groups[] = {
+#if CONFIG(SKYLAKE_SOC_PCH_H)
    { .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
    { .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8 },
    /* Sunrise Point PCH-H actually only has 4 ports in the
@@ -46,6 +41,11 @@
       and probing 4 non-existent ports shouldn't hurt. */
    { .slot = PCH_DEV_SLOT_PCIE_2,	.count = 8 },
    { 0 }
+#else
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4 },
+	{ 0 }
+#endif
 };

#if CONFIG(HAVE_ACPI_TABLES)
@@ -179,10 +179,7 @@
    itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);

/* swap enabled PCI ports in device tree if needed */
-	if (CONFIG(SKYLAKE_SOC_PCH_H))
-		pcie_rp_update_devicetree(pch_h_rp_groups);
-	else
-		pcie_rp_update_devicetree(pch_lp_rp_groups);
+	pcie_rp_update_devicetree(pch_rp_groups);
 }

static struct device_operations pci_domain_ops = {