Hello Matt Papageorge,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/41804
to review the following change.
Change subject: soc/amd/picasso: Install AGESA ACPI tables ......................................................................
soc/amd/picasso: Install AGESA ACPI tables
AGESA FSP provides additional ACPI tables that are required.
BUG=b:133337564, b:153675915 TEST=Boot trembyle to OS and dump ACPI tables. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xcc513000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cc635af0 Searching for AGESA FSP ACPI Tables ACPI: * SSDT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * CRAT (AGESA). ACPI: added table 7/32, length now 64 ACPI: * ALIB (AGESA). ACPI: added table 8/32, length now 68 ACPI: * IVRS (AGESA). ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at cc63ca30 ACPI: added table 11/32, length now 80 ACPI: done. ACPI tables: 102048 bytes.
[ 0.042326] ACPI: Early table checksum verification disabled [ 0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) [ 0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110) [ 0.083488] ACPI: FACS 0x00000000CC631240 000040 [ 0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110) [ 0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) [ 0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) [ 0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) [ 0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD AMD IVRS 00000001 AMD 00000000) [ 0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110)
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/include/soc/acpi.h M src/vendorcode/amd/fsp/picasso/FspGuids.h A src/vendorcode/amd/fsp/picasso/acpi_hob.h 6 files changed, 86 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/41804/1
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d0046ea..2b7cf28 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += root_complex.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += gpio.c ramstage-y += southbridge.c ramstage-y += pmutil.c diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c new file mode 100644 index 0000000..5aafd55 --- /dev/null +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi_hob.h> +#include <console/console.h> +#include <fsp/util.h> +#include <FspGuids.h> +#include <lib.h> +#include <soc/acpi.h> + +static uintptr_t add_agesa_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, + uintptr_t current) +{ + const struct amd_fsp_acpi_hob_info *data; + void *table = (void *)current; + size_t hob_size; + + data = fsp_find_extension_hob_by_guid(guid.b, &hob_size); + if (!data) { + printk(BIOS_ERR, "AGESA %s ACPI table was not found.\n", name); + return current; + } + + printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); + + memcpy(table, data->hob_payload, data->table_size_in_bytes); + + current += data->table_size_in_bytes; + acpi_add_table(rsdp, table); + current = acpi_align_current(current); + + return current; +} + +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp) +{ + printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n"); + + current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_CRAT_HOB_GUID, "CRAT", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_IVRS_HOB_GUID, "IVRS", rsdp, current); + + /* Add SRAT, MSCT, SLIT if needed in the future */ + + return current; +} diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f593664..61ba5e0 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -145,6 +145,8 @@
static void soc_init(void *chip_info) { + default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; + fsp_silicon_init(acpi_is_wakeup_s3());
data_fabric_set_mmio_np(); diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 6250f86..77f836c 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -14,6 +14,9 @@
void southbridge_inject_dsdt(const struct device *device);
+uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp); + const char *soc_acpi_name(const struct device *dev);
#endif /* __SOC_PICASSO_ACPI_H__ */ diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h index 24b185d..64bf97c 100644 --- a/src/vendorcode/amd/fsp/picasso/FspGuids.h +++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h @@ -9,6 +9,22 @@ GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c)
+#define AMD_FSP_ACPI_SSDT_HOB_GUID \ + GUID_INIT(0x54445353, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_CRAT_HOB_GUID \ + GUID_INIT(0x54415243, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_ALIB_HOB_GUID \ + GUID_INIT(0x42494c41, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_IVRS_HOB_GUID \ + GUID_INIT(0x53525649, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + #define PICASSO_MISC_DATA_HOB_GUID \ GUID_INIT(0xf2784616, 0xb9bf, 0x4e1e, \ 0x99, 0xe0, 0x96, 0x26, 0xda, 0x7e, 0xa5, 0xf5) diff --git a/src/vendorcode/amd/fsp/picasso/acpi_hob.h b/src/vendorcode/amd/fsp/picasso/acpi_hob.h new file mode 100644 index 0000000..b33ea50 --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/acpi_hob.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PI_PICASSO_ACPI_HOB_H__ +#define __PI_PICASSO_ACPI_HOB_H__ + +#include <stdint.h> + +struct amd_fsp_acpi_hob_info { + uint32_t table_size_in_bytes; + uint8_t total_hobs_for_table; + uint8_t sequence_number; + uint16_t reserved; + uint16_t hob_payload[0xffc8]; +} __packed; + +#endif /* __PI_PICASSO_ACPI_HOB_H__ */
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41804 )
Change subject: soc/amd/picasso: Install AGESA ACPI tables ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41804/1/src/soc/amd/picasso/agesa_a... File src/soc/amd/picasso/agesa_acpi.c:
https://review.coreboot.org/c/coreboot/+/41804/1/src/soc/amd/picasso/agesa_a... PS1, Line 40: current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current); I'm fundamentally against using any ACPI tables from a blob... it's so wrong, and we know the IVRS table is wrong.
https://review.coreboot.org/c/coreboot/+/41804/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/acpi_hob.h:
https://review.coreboot.org/c/coreboot/+/41804/1/src/vendorcode/amd/fsp/pica... PS1, Line 14: } __packed; Is there a reason to put this in a header vs the only consumer compilation unit?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41804 )
Change subject: soc/amd/picasso: Install AGESA ACPI tables ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41804/1/src/soc/amd/picasso/agesa_a... File src/soc/amd/picasso/agesa_acpi.c:
https://review.coreboot.org/c/coreboot/+/41804/1/src/soc/amd/picasso/agesa_a... PS1, Line 8: include <lib.h> looks like it is not used. I didn't checked the others
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41804 )
Change subject: soc/amd/picasso: Install AGESA ACPI tables ......................................................................
Uploaded patch set 2.
(3 comments)
https://review.coreboot.org/c/coreboot/+/41804/1/src/soc/amd/picasso/agesa_a... File src/soc/amd/picasso/agesa_acpi.c:
https://review.coreboot.org/c/coreboot/+/41804/1/src/soc/amd/picasso/agesa_a... PS1, Line 8: include <lib.h>
looks like it is not used. […]
You are right. I had a hexdump in here previously.
https://review.coreboot.org/c/coreboot/+/41804/1/src/soc/amd/picasso/agesa_a... PS1, Line 40: current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current);
I'm fundamentally against using any ACPI tables from a blob... […]
Filed b/157647314 to revisit this.
https://review.coreboot.org/c/coreboot/+/41804/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/acpi_hob.h:
https://review.coreboot.org/c/coreboot/+/41804/1/src/vendorcode/amd/fsp/pica... PS1, Line 14: } __packed;
Is there a reason to put this in a header vs the only consumer compilation unit?
Moved it.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Aaron Durbin, Matt Papageorge, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41804
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Install AGESA ACPI tables ......................................................................
soc/amd/picasso: Install AGESA ACPI tables
AGESA FSP provides additional ACPI tables that are required.
BUG=b:133337564, b:153675915 TEST=Boot trembyle to OS and dump ACPI tables. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xcc513000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cc635af0 Searching for AGESA FSP ACPI Tables ACPI: * SSDT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * CRAT (AGESA). ACPI: added table 7/32, length now 64 ACPI: * ALIB (AGESA). ACPI: added table 8/32, length now 68 ACPI: * IVRS (AGESA). ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at cc63ca30 ACPI: added table 11/32, length now 80 ACPI: done. ACPI tables: 102048 bytes.
[ 0.042326] ACPI: Early table checksum verification disabled [ 0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) [ 0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110) [ 0.083488] ACPI: FACS 0x00000000CC631240 000040 [ 0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110) [ 0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) [ 0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) [ 0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) [ 0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD AMD IVRS 00000001 AMD 00000000) [ 0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110)
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/include/soc/acpi.h M src/vendorcode/amd/fsp/picasso/FspGuids.h 5 files changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/41804/2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41804 )
Change subject: soc/amd/picasso: Install AGESA ACPI tables ......................................................................
Patch Set 2: Code-Review+2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41804 )
Change subject: soc/amd/picasso: Install AGESA ACPI tables ......................................................................
Patch Set 2: Code-Review+1
this should really be reworked so that coreboot generates the ACPI tables and not FSP/AGESA, but for bringup I can live with this; can't say that I like it though
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41804 )
Change subject: soc/amd/picasso: Install AGESA ACPI tables ......................................................................
soc/amd/picasso: Install AGESA ACPI tables
AGESA FSP provides additional ACPI tables that are required.
BUG=b:133337564, b:153675915 TEST=Boot trembyle to OS and dump ACPI tables. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xcc513000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cc635af0 Searching for AGESA FSP ACPI Tables ACPI: * SSDT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * CRAT (AGESA). ACPI: added table 7/32, length now 64 ACPI: * ALIB (AGESA). ACPI: added table 8/32, length now 68 ACPI: * IVRS (AGESA). ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at cc63ca30 ACPI: added table 11/32, length now 80 ACPI: done. ACPI tables: 102048 bytes.
[ 0.042326] ACPI: Early table checksum verification disabled [ 0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) [ 0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110) [ 0.083488] ACPI: FACS 0x00000000CC631240 000040 [ 0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110) [ 0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) [ 0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) [ 0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) [ 0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD AMD IVRS 00000001 AMD 00000000) [ 0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110)
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41804 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/include/soc/acpi.h M src/vendorcode/amd/fsp/picasso/FspGuids.h 5 files changed, 77 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Felix Held: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d62ccda..ce0a7a8 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += root_complex.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += gpio.c ramstage-y += southbridge.c ramstage-y += pmutil.c diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c new file mode 100644 index 0000000..fb168a1 --- /dev/null +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <fsp/util.h> +#include <FspGuids.h> +#include <soc/acpi.h> +#include <stdint.h> + +struct amd_fsp_acpi_hob_info { + uint32_t table_size_in_bytes; + uint8_t total_hobs_for_table; + uint8_t sequence_number; + uint16_t reserved; + uint16_t hob_payload[0xffc8]; +} __packed; + +static uintptr_t add_agesa_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, + uintptr_t current) +{ + const struct amd_fsp_acpi_hob_info *data; + void *table = (void *)current; + size_t hob_size; + + data = fsp_find_extension_hob_by_guid(guid.b, &hob_size); + if (!data) { + printk(BIOS_ERR, "AGESA %s ACPI table was not found.\n", name); + return current; + } + + printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); + + memcpy(table, data->hob_payload, data->table_size_in_bytes); + + current += data->table_size_in_bytes; + acpi_add_table(rsdp, table); + current = acpi_align_current(current); + + return current; +} + +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp) +{ + printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n"); + + current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_CRAT_HOB_GUID, "CRAT", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_IVRS_HOB_GUID, "IVRS", rsdp, current); + + /* Add SRAT, MSCT, SLIT if needed in the future */ + + return current; +} diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 4ea962f..7c6e6fb 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -143,6 +143,8 @@
static void soc_init(void *chip_info) { + default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; + fsp_silicon_init(acpi_is_wakeup_s3());
data_fabric_set_mmio_np(); diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 6250f86..77f836c 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -14,6 +14,9 @@
void southbridge_inject_dsdt(const struct device *device);
+uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp); + const char *soc_acpi_name(const struct device *dev);
#endif /* __SOC_PICASSO_ACPI_H__ */ diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h index 24b185d..64bf97c 100644 --- a/src/vendorcode/amd/fsp/picasso/FspGuids.h +++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h @@ -9,6 +9,22 @@ GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c)
+#define AMD_FSP_ACPI_SSDT_HOB_GUID \ + GUID_INIT(0x54445353, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_CRAT_HOB_GUID \ + GUID_INIT(0x54415243, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_ALIB_HOB_GUID \ + GUID_INIT(0x42494c41, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_IVRS_HOB_GUID \ + GUID_INIT(0x53525649, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + #define PICASSO_MISC_DATA_HOB_GUID \ GUID_INIT(0xf2784616, 0xb9bf, 0x4e1e, \ 0x99, 0xe0, 0x96, 0x26, 0xda, 0x7e, 0xa5, 0xf5)
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41804 )
Change subject: soc/amd/picasso: Install AGESA ACPI tables ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4673 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4672 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4671 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4670
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Aaron Durbin (Code Review)
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Felix Held (Code Review)
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HAOUAS Elyes (Code Review)
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Raul Rangel (Code Review)