Change in coreboot[master]: nb/amd/amdfam10/bootblock.c: Change to standard PCI access functions

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62092 )

Change subject: nb/amd/amdfam10/bootblock.c: Change to standard PCI access functions
......................................................................

nb/amd/amdfam10/bootblock.c: Change to standard PCI access functions

The comment about MMCONF not being ready is no longer true. PCI MMCONF
is set up right after BSP is out of CAR reset in the bootblock C entry.
Change all PCI accessors to use generic pci_{read,write}_config instead
of explicit I/O accesses.

Signed-off-by: Michał Żygowski 
Change-Id: Ifae7d6e16daa072f841704fa634fea40e1470856
---
M src/northbridge/amd/amdfam10/bootblock.c
1 file changed, 16 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/62092/1

diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c
index f504355..ac28334 100644
--- a/src/northbridge/amd/amdfam10/bootblock.c
+++ b/src/northbridge/amd/amdfam10/bootblock.c
@@ -20,7 +20,6 @@
 #include <device/pci_def.h>

// For SB HT chain only
-// mmconf is not ready yet
 static void set_bsp_node_CHtExtNodeCfgEn(void)
 {
    u32 dword;
@@ -28,7 +27,7 @@
    if (!CONFIG(EXT_RT_TBL_SUPPORT))
    	return;

-	dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
+	dword = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
    dword |= (1<<27) | (1<<25);
    /* CHtExtNodeCfgEn: coherent link extended node configuration enable,
       Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0]
@@ -38,7 +37,7 @@
     */

/* CHtExtAddrEn */
-	pci_io_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword);
+	pci_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword);
    // CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB.
 }

@@ -70,7 +69,7 @@
    	u8 hdr_type, pos;
    	last_unitid = next_unitid;

-		id = pci_io_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
+		id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
    	/* If the chain is enumerated quit */
    	if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
    		(((id >> 16) & 0xffff) == 0xffff) ||
@@ -79,26 +78,26 @@
    		break;
    	}

-		hdr_type = pci_io_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
+		hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
    	pos = 0;
    	hdr_type &= 0x7f;

if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
    		(hdr_type == PCI_HEADER_TYPE_BRIDGE))
    	{
-			pos = pci_io_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
+			pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
    	}
    	while (pos != 0) {
    		u8 cap;
-			cap = pci_io_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
+			cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
    		if (cap == PCI_CAP_ID_HT) {
    			u16 flags;
    			/* Read and write and reread flags so the link
    			 * direction bit is valid.
    			 */
-				flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
-				pci_io_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags);
-				flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
+				flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
+				pci_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags);
+				flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
    			if ((flags >> 13) == 0) {
    				unsigned int count;
    				unsigned int ctrl, ctrl_off;
@@ -129,14 +128,14 @@
    				devx = PCI_DEV(0, next_unitid, 0);
    				next_unitid += count;

-					pci_io_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
+					pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);

/* Test for end of chain */
    				ctrl_off = ((flags >> 10) & 1)?
    					PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;

do {
-						ctrl = pci_io_read_config16(devx, pos + ctrl_off);
+						ctrl = pci_read_config16(devx, pos + ctrl_off);
    					/* Is this the end of the hypertransport chain? */
    					if (ctrl & (1 << 6)) {
    						goto out;
@@ -151,8 +150,8 @@
    						 * if its transient
    						 */
    						ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-							pci_io_write_config16(devx, pos + ctrl_off, ctrl);
-							ctrl = pci_io_read_config16(devx, pos + ctrl_off);
+							pci_write_config16(devx, pos + ctrl_off, ctrl);
+							ctrl = pci_read_config16(devx, pos + ctrl_off);
    						if (ctrl & ((1 << 4) | (1 << 8))) {
    							// can not clear the error
    							break;
@@ -163,7 +162,7 @@
    				break;
    			}
    		}
-			pos = pci_io_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
+			pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
    	}
    } while (last_unitid != next_unitid);

@@ -172,10 +171,10 @@
    	if ((ht_dev_num > 1) && 
    	    (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
    		u16 flags;
-			flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
+			flags = pci_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
    		flags &= ~0x1f;
    		flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
-			pci_io_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
+			pci_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
    	}
    }
 }