[XS] Change in coreboot[main]: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly

[Paul Menzel (Code Review)]

Attention is currently required from: Eran Mitrani, Eric Lai, Kane Chen, Kapil Porwal, Ravishankar Sarawadi, Tarun.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78252?usp=email )

The change is no longer submittable: All-Comments-Resolved is unsatisfied now.

Change subject: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly
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Patch Set 2:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/78252/comment/20cd9659_c3b4299c :
PS2, Line 10: code requires
… code that requires …?

https://review.coreboot.org/c/coreboot/+/78252/comment/73600659_e5083fa1 :
PS2, Line 11: insrc/soc/intel/common/acpi/pcie_clk.asl
Missing space after *in*.

https://review.coreboot.org/c/coreboot/+/78252/comment/cde0a920_6b43dd78 :
PS2, Line 13: TEST=suspend_stress_test 50 cycle pass, type-c display OK on screebo
Did it also succeed before your change?