Change in ...coreboot[master]: cpu/intel/model_2065x: Put stage cache in TSEG

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/26298 )

Change subject: cpu/intel/model_2065x: Put stage cache in TSEG
......................................................................

cpu/intel/model_2065x: Put stage cache in TSEG

TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.

Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/intel/model_2065x/Makefile.inc
M src/cpu/intel/model_2065x/model_2065x.h
A src/cpu/intel/model_2065x/stage_cache.c
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/nehalem/ram_calc.c
6 files changed, 63 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 707713c..d8c0168 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -21,6 +21,7 @@
    select CPU_INTEL_COMMON
    select NO_FIXED_XIP_ROM_SIZE
    select PARALLEL_MP
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM

config BOOTBLOCK_CPU_INIT
    string
@@ -30,4 +31,8 @@
    hex
    default 0x800000

+config SMM_RESERVED_SIZE
+	hex
+	default 0x100000
+
 endif
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 043141a..39246c0 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -19,6 +19,10 @@

smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c

+romstage-y += stage_cache.c
+ramstage-y += stage_cache.c
+postcar-y += stage_cache.c
+
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin

cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index 904e794..e7ba2a7 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -80,4 +80,22 @@
 int cpu_config_tdp_levels(void);
 #endif

+/*
+ * Region of SMM space is reserved for multipurpose use. It falls below
+ * the IED region and above the SMM handler.
+ */
+#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
+#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE)
+
+/* Sanity check config options. */
+#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE)
+# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE"
+#endif
+#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
+# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
+#endif
+#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
+# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
+#endif
+
 #endif
diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c
new file mode 100644
index 0000000..ab8ac97
--- /dev/null
+++ b/src/cpu/intel/model_2065x/stage_cache.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <stage_cache.h>
+#include <cpu/intel/smm/gen1/smi.h>
+#include "model_2065x.h"
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	/*
+	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+	 * The top of RAM is defined to be the TSEG base address.
+	 */
+	*size = RESERVED_SMM_SIZE;
+	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
+			 + RESERVED_SMM_OFFSET);
+}
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 233b0bb..485cb27 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -171,13 +171,6 @@
    add_fixed_resources(dev, 10);
 }

-u32 northbridge_get_tseg_base(void)
-{
-	struct device *dev = pcidev_on_root(0, 0);
-
-	return pci_read_config32(dev, TSEG) & ~1;
-}
-
 u32 northbridge_get_tseg_size(void)
 {
    return CONFIG_SMM_TSEG_SIZE;
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index 163f21c..ca821da 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -23,6 +23,7 @@
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
+#include <cpu/intel/smm/gen1/smi.h>
 #include "nehalem.h"

static uintptr_t smm_region_start(void)
@@ -32,6 +33,11 @@
    return tom;
 }

+u32 northbridge_get_tseg_base(void)
+{
+	return (u32)smm_region_start & ~1;
+}
+
 void *cbmem_top(void)
 {
    return (void *) smm_region_start();