Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74786 )
Change subject: mb/google/brya/var/taeko: Disable C1E for RPL CPU ......................................................................
mb/google/brya/var/taeko: Disable C1E for RPL CPU
Disable C1E on RPL CPU for improving acoustic noise tests
BUG=b:278654939 TEST:emerge-brya coreboot and check that C1E can be disabled on RPL CPU
Signed-off-by: Joey Peng joey.peng@lcfc.corp-partner.google.com Change-Id: I5e4c74aa288f1c824c5e7ce83090cf61d7653183 --- M src/mainboard/google/brya/variants/taeko/variant.c 1 file changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/74786/1
diff --git a/src/mainboard/google/brya/variants/taeko/variant.c b/src/mainboard/google/brya/variants/taeko/variant.c index b44e9e3..4defc98 100644 --- a/src/mainboard/google/brya/variants/taeko/variant.c +++ b/src/mainboard/google/brya/variants/taeko/variant.c @@ -1,9 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <fw_config.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/cpu_ids.h> #include <sar.h>
const char *get_wifi_sar_cbfs_filename(void) { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); } + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + //Disable C1E for RPL CPU + + uint32_t cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_RAPTORLAKE_P_J0 || cpu_id == CPUID_RAPTORLAKE_P_Q0) { + config->c1e = 0; + printk(BIOS_INFO, "Disable C1E for RPL CPU\n"); + } + else if (cpu_id == CPUID_ALDERLAKE_R0) { + config->c1e = 1; + printk(BIOS_INFO, "Keep C1E enabled for ADL CPU\n"); + } +}