Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71643 )
Change subject: soc/intel/meteorlake: Fill PCI SSID parameters ......................................................................
soc/intel/meteorlake: Fill PCI SSID parameters
BUG=none TEST=Verify that SSID for all PCI devices is same as their respective DIDs.
Output of lspci in OS: 00:00.0 Host bridge [0600]: Intel Corporation Device [8086:7d01] Subsystem: Intel Corporation Device [8086:7d01] 00:02.0 VGA compatible controller [0300]: Intel Corporation Device [8086:7d55] (prog-if 00 [VGA controller]) Subsystem: Intel Corporation Device [8086:7d55] 00:04.0 Signal processing controller [1180]: Intel Corporation Device [8086:7d03] Subsystem: Intel Corporation Device [8086:7d03] 00:05.0 Multimedia controller [0480]: Intel Corporation Device [8086:7d19] Subsystem: Intel Corporation Device [8086:7d19] 00:06.0 PCI bridge [0604]: Intel Corporation Device [8086:7e4d] (prog-if 00 [Normal decode]) Capabilities: [98] Subsystem: Intel Corporation Device [8086:7e4d] 00:07.0 PCI bridge [0604]: Intel Corporation Device [8086:7ec4] (prog-if 00 [Normal decode]) Capabilities: [90] Subsystem: Intel Corporation Device [8086:7ec4] 00:07.2 PCI bridge [0604]: Intel Corporation Device [8086:7ec6] (prog-if 00 [Normal decode]) Capabilities: [90] Subsystem: Intel Corporation Device [8086:7ec6] 00:0a.0 Signal processing controller [1180]: Intel Corporation Device [8086:7d0d] (rev 01) Subsystem: Intel Corporation Device [8086:7d0d] 00:0d.0 USB controller [0c03]: Intel Corporation Device [8086:7ec0] (prog-if 30 [XHCI]) Subsystem: Intel Corporation Device [8086:7ec0] 00:0d.2 USB controller [0c03]: Intel Corporation Device [8086:7ec2] (prog-if 40 [USB4 Host Interface]) Subsystem: Intel Corporation Device [8086:7ec2] 00:0d.3 USB controller [0c03]: Intel Corporation Device [8086:7ec3] (prog-if 40 [USB4 Host Interface]) Subsystem: Intel Corporation Device [8086:7ec3] 00:14.0 USB controller [0c03]: Intel Corporation Device [8086:7e7d] (prog-if 30 [XHCI]) Subsystem: Intel Corporation Device [8086:7e7d] 00:14.2 RAM memory [0500]: Intel Corporation Device [8086:7e7f] Subsystem: Intel Corporation Device [8086:7e7f] 00:14.3 Network controller [0280]: Intel Corporation Device [8086:7e40] Subsystem: Intel Corporation Device [8086:0094] 00:15.0 Serial bus controller [0c80]: Intel Corporation Device [8086:7e78] Subsystem: Intel Corporation Device [8086:7e78] 00:15.1 Serial bus controller [0c80]: Intel Corporation Device [8086:7e79] Subsystem: Intel Corporation Device [8086:7e79] 00:15.3 Serial bus controller [0c80]: Intel Corporation Device [8086:7e7b] Subsystem: Intel Corporation Device [8086:7e7b] 00:16.0 Communication controller [0780]: Intel Corporation Device [8086:7e70] Subsystem: Intel Corporation Device [8086:7e70] 00:19.0 Serial bus controller [0c80]: Intel Corporation Device [8086:7e50] Subsystem: Intel Corporation Device [8086:7e50] 00:19.1 Serial bus controller [0c80]: Intel Corporation Device [8086:7e51] Subsystem: Intel Corporation Device [8086:7e51] 00:1c.0 PCI bridge [0604]: Intel Corporation Device [8086:7e3c] (prog-if 00 [Normal decode]) Capabilities: [98] Subsystem: Intel Corporation Device [8086:7e3c] 00:1c.5 PCI bridge [0604]: Intel Corporation Device [8086:7e3d] (prog-if 00 [Normal decode]) Capabilities: [98] Subsystem: Intel Corporation Device [8086:7e3d] 00:1c.6 PCI bridge [0604]: Intel Corporation Device [8086:7e3e] (prog-if 00 [Normal decode]) Capabilities: [98] Subsystem: Intel Corporation Device [8086:7e3e] 00:1e.0 Communication controller [0780]: Intel Corporation Device [8086:7e25] Subsystem: Intel Corporation Device [8086:7e25] 00:1e.3 Serial bus controller [0c80]: Intel Corporation Device [8086:7e30] Subsystem: Intel Corporation Device [8086:7e30] 00:1f.0 ISA bridge [0601]: Intel Corporation Device [8086:7e01] Subsystem: Intel Corporation Device [8086:7e01] 00:1f.3 Multimedia audio controller [0401]: Intel Corporation Device [8086:7e28] 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] Subsystem: Intel Corporation Device [8086:7e23]
Signed-off-by: Kapil Porwal kapilporwal@google.com Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 141 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/71643/1
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index d40779a..2e1baa5 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -456,6 +456,75 @@ fsp_debug_event_handler; }
+static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid) +{ + if(dev && svid && ssid) { + if (CONFIG_SUBSYSTEM_VENDOR_ID) + *svid = CONFIG_SUBSYSTEM_VENDOR_ID; + else + *svid = dev->subsystem_vendor ? : 0x8086; + if (CONFIG_SUBSYSTEM_DEVICE_ID) + *ssid = CONFIG_SUBSYSTEM_DEVICE_ID; + else + *ssid = dev->subsystem_device ? : 0xFFFE; + } +} + +static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_meteorlake_config *config) +{ + /* + * Prevent FSP from programming write-once subsystem IDs by providing + * a custom SSID table. Must have at least one entry for the FSP to + * use the table. + */ + struct svid_ssid_init_entry { + union { + struct { + uint64_t reg:12; /* Register offset */ + uint64_t function:3; + uint64_t device:5; + uint64_t bus:8; + uint64_t :4; + uint64_t segment:16; + uint64_t :16; + }; + uint64_t segbusdevfuncregister; + }; + struct { + uint16_t svid; + uint16_t ssid; + }; + uint32_t reserved; + }; + + static struct svid_ssid_init_entry ssid_table[256]; + const struct device *dev; + int i = 0; + + for (dev = all_devices; dev; dev = dev->next) { + if (!(is_dev_enabled(dev) && + dev->path.type == DEVICE_PATH_PCI && + dev->bus->secondary == 0)) + continue; + if(dev->path.pci.devfn == PCI_DEVFN_ROOT) { + evaluate_ssid(dev, &s_cfg->SiCustomizedSvid, &s_cfg->SiCustomizedSsid); + } else { + ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; + ssid_table[i].device = PCI_SLOT(dev->path.pci.devfn); + ssid_table[i].function = PCI_FUNC(dev->path.pci.devfn); + evaluate_ssid(dev, &ssid_table[i].svid, &ssid_table[i].ssid); + i++; + } + } + + s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table; + s_cfg->SiNumberOfSsidTableEntry = i; + + /* Ensure FSP will program the registers */ + s_cfg->SiSkipSsidProgramming = 0; +} + static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_meteorlake_config *config) { @@ -484,6 +553,7 @@ fill_fsps_misc_power_params, fill_fsps_ufs_params, fill_fsps_ai_params, + fill_fsps_pci_ssid_params, };
for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)
-
Kapil Porwal (Code Review)