Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 )
Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38998/5/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:
https://review.coreboot.org/c/coreboot/+/38998/5/src/soc/intel/tigerlake/inc... PS5, Line 64: : /* Rcomp configuration information */ : struct rcomp_cfg { : /* Rcomp Resistor */ : uint16_t rcomp_resistor; : : /* Rcomp Target */ : uint16_t rcomp_target[NUM_RCOMP_TARGETS]; : : }; :
Why is this required? IIUC, based on discussions on partner bug, Rcomp values are not required to be […]
Rcomp values are not required for LPDDR4 but it is needed for DDR4 memory type. There are RVP's which have DDR4 memory and need it during DDR4 build. That's the reason I added this here.
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Srinidhi N Kaushik (Code Review)