the following patch was just integrated into master: commit 483ff8253943b134e5e07ac89d08e49fca1c28d8 Author: Patrick Georgi patrick.georgi@secunet.com Date: Tue Jun 18 11:34:01 2013 +0200
sandybridge: Store MRC cache in CBFS
Location is hard-coded right now, which isn't optimal. It must be chip erase block aligned, which might fail on some flash chips (it's 64k aligned which should work for most cases).
Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986 Signed-off-by: Patrick Georgi patrick.georgi@secunet.com Reviewed-on: http://review.coreboot.org/3497 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Patrick Georgi patrick@georgi-clan.de
See http://review.coreboot.org/3497 for details.
-gerrit