Change in coreboot[master]: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID

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Jonathan Kollasch (Code Review)

13 Feb 2020 13 Feb '20

11:08 a.m.

Jonathan Kollasch has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38865 )

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID ......................................................................

nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID

Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net --- M src/northbridge/intel/sandybridge/northbridge.c 1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38865/1

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index a9b1c25..d679eaa 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -472,6 +472,12 @@ .device = 0x0104, /* Sandy bridge */ };

+static const struct pci_driver mc_driver_108 __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0108, /* Sandy bridge */ +}; + static const struct pci_driver mc_driver_150 __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL,

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Jonathan Kollasch (Code Review)

13 Feb 13 Feb

4:14 p.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38865

to look at the new patch set (#2).

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID ......................................................................

nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38865/2

Paul Menzel (Code Review)

14 Feb 14 Feb

10:38 a.m.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38865 )

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID ......................................................................

Patch Set 2: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/38865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Gerrit-Change-Number: 38865 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Fri, 14 Feb 2020 13:38:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Patrick Rudolph (Code Review)

11:12 a.m.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38865 )

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID ......................................................................

Patch Set 2: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/38865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Gerrit-Change-Number: 38865 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Fri, 14 Feb 2020 14:12:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Angel Pons (Code Review)

18 Feb 18 Feb

6:09 a.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38865 )

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID ......................................................................

Patch Set 2: Code-Review+1

(1 comment)

You probably want to re-upload this so that the build bot verifies it. While you're at it, there's a minor thing.

https://review.coreboot.org/c/coreboot/+/38865/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/northbridge.c:

https://review.coreboot.org/c/coreboot/+/38865/2/src/northbridge/intel/sandy... PS2, Line 464: That's a tab, should be a space.

-- To view, visit https://review.coreboot.org/c/coreboot/+/38865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Gerrit-Change-Number: 38865 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Tue, 18 Feb 2020 09:09:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Jonathan Kollasch (Code Review)

10:13 a.m.

Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38865

to look at the new patch set (#3).

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID ......................................................................

nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38865/3

-- To view, visit https://review.coreboot.org/c/coreboot/+/38865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Gerrit-Change-Number: 38865 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: newpatchset

Patrick Georgi (Code Review)

11:55 a.m.

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38865 )

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID ......................................................................

Patch Set 3: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/38865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Gerrit-Change-Number: 38865 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Tue, 18 Feb 2020 14:55:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Patrick Georgi (Code Review)

11:56 a.m.

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38865 )

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID ......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38865/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/northbridge.c:

https://review.coreboot.org/c/coreboot/+/38865/2/src/northbridge/intel/sandy... PS2, Line 464:

...

That's a tab, should be a space.

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/38865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Gerrit-Change-Number: 38865 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Tue, 18 Feb 2020 14:56:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Patrick Georgi (Code Review)

11:56 a.m.

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38865 )

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID ......................................................................

nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID

Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/38865 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/northbridge/intel/sandybridge/northbridge.c 1 file changed, 1 insertion(+), 1 deletion(-)

Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 68f8411..cc8a62c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -461,7 +461,7 @@ };

static const unsigned short pci_device_ids[] = { - 0x0100, 0x0104, /* Sandy Bridge */ + 0x0100, 0x0104, 0x0108, /* Sandy Bridge */ 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ 0 };

-- To view, visit https://review.coreboot.org/c/coreboot/+/38865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Gerrit-Change-Number: 38865 Gerrit-PatchSet: 4 Gerrit-Owner: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Jonathan Kollasch jakllsch@kollasch.net Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: merged

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Angel Pons (Code Review)
Jonathan Kollasch (Code Review)
Patrick Georgi (Code Review)
Patrick Rudolph (Code Review)
Paul Menzel (Code Review)