Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33769
Change subject: soc/amd/picasso: Update machine check support ......................................................................
soc/amd/picasso: Update machine check support
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: Iae48a0c3fb2abf2aa3fb78af8d50431c8533f76f --- M src/soc/amd/picasso/mca.c 1 file changed, 1 insertion(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/33769/1
diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 8a875d9..57fa9c6 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -97,11 +97,6 @@ * which is the best method to report MSR context. As a result, add two * structures: A "processor generic error" that is parsed, and an IA32/X64 one * to capture complete information. - * - * Future work may attempt to interpret the specific Family 15h error symptoms - * found in the MCA registers. This data could enhance the reporting of the - * Processor Generic section and the failing error/check added to the - * IA32/X64 section. */ static void build_bert_mca_error(struct mca_bank *mci) { @@ -161,6 +156,7 @@ "Floating point unit" };
+/* Check the Legacy Machine Check Architecture registers */ void check_mca(void) { int i; @@ -173,9 +169,6 @@
if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) { - if (i == 3) /* Reserved in Family 15h */ - continue; - mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24;
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33769 )
Change subject: soc/amd/picasso: Update machine check support ......................................................................
Patch Set 4: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33769 )
Change subject: soc/amd/picasso: Update machine check support ......................................................................
soc/amd/picasso: Update machine check support
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: Iae48a0c3fb2abf2aa3fb78af8d50431c8533f76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33769 Reviewed-by: Martin Roth martinroth@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/mca.c 1 file changed, 1 insertion(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 8a875d9..57fa9c6 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -97,11 +97,6 @@ * which is the best method to report MSR context. As a result, add two * structures: A "processor generic error" that is parsed, and an IA32/X64 one * to capture complete information. - * - * Future work may attempt to interpret the specific Family 15h error symptoms - * found in the MCA registers. This data could enhance the reporting of the - * Processor Generic section and the failing error/check added to the - * IA32/X64 section. */ static void build_bert_mca_error(struct mca_bank *mci) { @@ -161,6 +156,7 @@ "Floating point unit" };
+/* Check the Legacy Machine Check Architecture registers */ void check_mca(void) { int i; @@ -173,9 +169,6 @@
if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) { - if (i == 3) /* Reserved in Family 15h */ - continue; - mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24;