Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45290 )
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
mb/intel/tglrvp: Add DTT support for tglrvp
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control.
BRANCH=None BUG=Noe TEST=Build and boot on tglrvp board
Change-Id: I4158ab85f7863378d46b957e49f97aeaa96492f5 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M Documentation/soc/amd/family17h.md M src/include/device/pci.h M src/lib/Makefile.inc M src/mainboard/amd/mandolin/Makefile.inc M src/mainboard/google/trogdor/boardid.c M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/zork/spd/Makefile.inc M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/amd/picasso/Makefile.inc M src/soc/intel/tigerlake/include/soc/systemagent.h M util/abuild/abuild 13 files changed, 136 insertions(+), 91 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45290/1
diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index 23088cd..fffe25b 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -240,47 +240,12 @@ ## APCB setup
APCBs are used to provide the PSP with SPD information and optionally a set of -GPIOs to use for selecting which SPD to load. - -### Prebuilt -The picasso `Makefile` expects APCBs to be located in -`3rdparty/blobs/mainboard/$(MAINBOARDDIR)`. If you have a pre-built binary just -add the following to your mainboard's Makefile. - -``` -# i.e., 3rdparty/blobs/mainboard/amd/mandolin/APCB_mandolin.bin -APCB_SOURCES = mandolin -``` +GPIOs to use for selecting which SPD to load. A list of APCB files should be +specified in `APCB_SOURCES`.
### Generating APCBs If you have a template APCB file, the `apcb_edit` tool can be used to inject the -SPD and GPIOs used to select the correct slot. Entries should match this -pattern `{NAME}_x{1,2}`. There should be a matching SPD hex file in -`SPD_SOURCES_DIR` matching the pattern `{NAME}.spd.hex`. -The `_x{1,2}` suffix denotes single or dual channel. Up to 16 slots can be used. -If a slot is empty, the special empty keyword can be used. This will generate -an APCB with an empty SPD. - -``` -APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 -APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 -APCB_SOURCES += empty # 0b0010 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0011 -``` - -#### APCB Board ID GPIO configuration. -The GPIOs determine which memory SPD will be used during boot. -``` -# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL -# GPIO_NUMBER: FCH GPIO number -# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO -# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO - -APCB_BOARD_ID_GPIO0 = 121 1 0 -APCB_BOARD_ID_GPIO1 = 120 1 0 -APCB_BOARD_ID_GPIO2 = 131 3 0 -APCB_BOARD_ID_GPIO3 = 116 1 0 -``` +SPD and GPIOs used to select the correct slot.
## Footnotes
diff --git a/src/include/device/pci.h b/src/include/device/pci.h index ec3d45e..6e28cb7 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -133,7 +133,7 @@ #if ENV_PCI_SIMPLE_DEVICE void pci_dev_request_bus_master(pci_devfn_t dev) #else -void pci_dev_request_bus_master(const struct device *dev) +void pci_dev_request_bus_master(struct device *dev) #endif /* ENV_PCI_SIMPLE_DEVICE */ { if (CONFIG(PCI_ALLOW_BUS_MASTER)) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4ce133a..e23b9de 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -362,7 +362,7 @@ $(LIB_SPD_BIN): $(LIB_SPD_DEPS) for f in $(LIB_SPD_DEPS); \ do for c in $$(cat $$f | grep --binary-files=text -v ^#); \ - do printf $$(printf '%o' 0x$$c); \ + do printf $$(printf '\%o' 0x$$c); \ done; \ done > $@
diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 1865e74..6d7bf3a 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -10,8 +10,7 @@ ramstage-y += emmc_gpio.c endif
-# APCB_mandolin.bin -APCB_SOURCES = mandolin +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_mandolin.bin
PHONY+=add_mchp_fw INTERMEDIATE+=add_mchp_fw diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index f60dddbe..edde164 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -16,11 +16,12 @@ return id; }
-/* Whether a revision was built before or after the great pin migration of August 2020. */ +/* Some boards/revisions use one GPIO mapping and others use another. There's no real rhyme or + reason to it. Don't try to think about it too much... */ static bool use_old_pins(void) { return ((CONFIG(BOARD_GOOGLE_TROGDOR) && board_id() < 2) || - (CONFIG(BOARD_GOOGLE_LAZOR) && board_id() < 3) || + CONFIG(BOARD_GOOGLE_LAZOR) || (CONFIG(BOARD_GOOGLE_POMPOM) && board_id() < 1)); }
diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index c7fa706..7255423 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -125,7 +125,7 @@ /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE), /* F15 : GSXSRESET# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_F15, 1, DEEP), /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc index 66957d8..1042d91 100644 --- a/src/mainboard/google/zork/spd/Makefile.inc +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -2,3 +2,23 @@
# This directory SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd + +APCB_SOURCES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).gen) + +# APCB binary with magic numbers to be replaced by apcb_edit tool +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin + +$(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)/%.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --strip_manufacturer_information \ + --spd_0_0 $< \ + $(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index c94cca6..53df820 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -3,16 +3,19 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 + select DPTF_USE_EISA_HID select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_DTT select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH select EC_ACPI diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d4390b0..e254e37 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -115,6 +115,24 @@ # Enable S0ix register "s0ix_enable" = "1"
+ # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 38, + .tdp_pl4 = 71, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -149,7 +167,29 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up3 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7a5cae1..08c4245 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -109,6 +109,24 @@ # Enable S0ix register "s0ix_enable" = "1"
+ # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 66, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 40, + .tdp_pl4 = 83, + }" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -143,7 +161,29 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up3 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f4ec6c9..eb2be50 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -198,7 +198,7 @@ #
# type = 0x60 -PSP_APCB_FILES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).bin) +PSP_APCB_FILES=$(APCB_SOURCES)
# type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) @@ -383,28 +383,6 @@ --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE)
-# Copy prebuild APCBs if they exist -$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin - cp $< $@ - -# APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin - -$(obj)/APCB_%.bin: $$(SPD_SOURCES_DIR)/%.hex \ - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) \ - $@ \ - --hex \ - --strip_manufacturer_information \ - --spd_0_0 $< \ - $(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \ - --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ - --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ - --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ - --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) - $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ @@ -443,6 +421,7 @@ $$(PSP_APCB_FILES) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index fca9b2b..437356d 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,40 +15,40 @@
#define EPBAR 0x40 #define DMIBAR 0x68 -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23)
-#define BIOS_RESET_CPL 0x5da8 +/* MCHBAR offsets */ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 #define IPUVTBAR 0x7880 #define TBT0BAR 0x7888 #define TBT1BAR 0x7890 #define TBT2BAR 0x7898 #define TBT3BAR 0x78A0 + #define MAX_TBT_PCIE_PORT 4
-#define VTBAR_ENABLED 0x01 +#define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull
-#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define IMRBASE 0x6A40 -#define IMRLIMIT 0x6A48 - static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, };
#define V_P2SB_CFG_IBDF_BUS 0 diff --git a/util/abuild/abuild b/util/abuild/abuild index 53a988b9..7561495 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -263,10 +263,8 @@ # Disable all other payload config options { echo "# CONFIG_PAYLOAD_SEABIOS is not set" - echo "# CONFIG_PAYLOAD_BAYOU is not set" echo "# CONFIG_PAYLOAD_FILO is not set" echo "# CONFIG_PAYLOAD_GRUB2 is not set" - echo "# CONFIG_PAYLOAD_OPENBIOS is not set" echo "# CONFIG_PAYLOAD_DEPTHCHARGE is not set" echo "# CONFIG_PAYLOAD_LINUXBOOT is not set" echo "# CONFIG_PAYLOAD_UBOOT is not set"
Sumeet R Pawnikar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45290 )
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
Abandoned
sorry by mistake uploaded this.
-
Sumeet R Pawnikar (Code Review)