Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 )
Change subject: sc7180: Add QUPv3 FW load & config ......................................................................
Patch Set 44:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/in... File src/soc/qualcomm/sc7180/include/soc/qupv3_config.h:
https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/in... PS40, Line 54: #define QUPV3_UART_SRC_HZ 7372800
*ping* […]
*ping*
This was the outstanding request from patch set 40 that I mostly care about, please address this one.
https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/qu... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/qu... PS40, Line 75: /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */
UART driver can derive 115200 baud from any of the frequencies maintained by QUP clock table, usuall […]
I think you misunderstood the request. I'm fine with using 7372800Hz here, I'm just saying QcLib should not touch the clock or divisor configuration. It should just keep the settings that coreboot already configured. Baud rate in coreboot is configurable via Kconfig so it is not guaranteed to be 115200, and when it is something else we don't want QcLib to suddenly force it back to 115200 halfway through the boot.
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Julius Werner (Code Review)