HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/20397
Change subject: cpu/*: Add whitespace around '<<' ......................................................................
cpu/*: Add whitespace around '<<'
Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/amd/agesa/cache_as_ram.inc M src/cpu/amd/agesa/cache_as_ram_legacy.inc M src/cpu/amd/dualcore/amd_sibling.c M src/cpu/amd/dualcore/dualcore.c M src/cpu/amd/dualcore/dualcore_id.c M src/cpu/amd/geode_gx2/cpubug.c M src/cpu/amd/mtrr/amd_mtrr.c M src/cpu/amd/pi/cache_as_ram.inc M src/cpu/amd/quadcore/amd_sibling.c M src/cpu/intel/car/cache_as_ram_ht.inc M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/via/c7/c7_init.c M src/cpu/via/nano/nano_init.c 14 files changed, 28 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20397/1
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 857873a..8038177 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -40,7 +40,7 @@ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4
post_code(0xa1) diff --git a/src/cpu/amd/agesa/cache_as_ram_legacy.inc b/src/cpu/amd/agesa/cache_as_ram_legacy.inc index c0a69ec..5548007 100644 --- a/src/cpu/amd/agesa/cache_as_ram_legacy.inc +++ b/src/cpu/amd/agesa/cache_as_ram_legacy.inc @@ -43,7 +43,7 @@ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4
/* Get the cpu_init_detected */ diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 1c003c8..693ceb8 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -59,7 +59,7 @@ uint32_t val; dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); val = pci_read_config32(dev, 0x68); - val |= (1<<17)|(1<<18); + val |= (1 << 17)|(1 << 18); pci_write_config32(dev, 0x68, val); } } @@ -84,7 +84,7 @@
if (bsp_apic_id > 0) { // IOAPIC could start from 0 return 0; - } else if (pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0 + } else if (pci_read_config32(dev, 0x68) & ( (1 << 17) | (1 << 18)) ) { // enabled ext id but bsp = 0 return 1; }
diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 83302ca..1f25668 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -48,11 +48,11 @@ uint32_t dword; // set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44); - dword |= 1<<27; // NbMcaToMstCpuEn bit + dword |= 1 << 27; // NbMcaToMstCpuEn bit pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword); // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68); - dword |= 1<<5; + dword |= 1 << 5; pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword); }
diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 80ce1c7..e7af552 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -43,14 +43,14 @@ // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] id.coreid = (cpuid_ebx(1) >> 24) & 0xf; id.nodeid = (id.coreid>>CORE_ID_BIT); - id.coreid &= ((1<<CORE_ID_BIT)-1); + id.coreid &= ((1 << CORE_ID_BIT)-1); } else { // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27] id.nodeid = (cpuid_ebx(1) >> 24) & 0xf; id.coreid = (id.nodeid>>NODE_ID_BIT); - id.nodeid &= ((1<<NODE_ID_BIT)-1); + id.nodeid &= ((1 << NODE_ID_BIT)-1); } return id; } diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c index af7ddf3..cf2b79d 100644 --- a/src/cpu/amd/geode_gx2/cpubug.c +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -54,8 +54,8 @@ * for PCI writes to complete. */ msr = rdmsr(CPU_DM_CONFIG0); - msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT); - msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT); + msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT); + msr.hi |= (2 << DM_CONFIG0_UPPER_WSREQ_SHIFT); msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; wrmsr(CPU_DM_CONFIG0, msr);
@@ -126,7 +126,7 @@ msr = rdmsr(MSR_GLCP+0x17); if ((msr.lo & 0xff) <= CPU_REV_2_0) { msr = rdmsr(GLCP_SYS_RSTPLL); - if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT)) + if (msr.lo & (1 << RSTPPL_LOWER_SDRMODE_SHIFT)) return; }
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 106cb79..8cb6658 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -54,8 +54,8 @@ "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", __func__, msr2.lo, msr2.hi);
- amd_topmem = (uint64_t) msr.hi<<32 | msr.lo; - amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; + amd_topmem = (uint64_t) msr.hi << 32 | msr.lo; + amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo; }
static void setup_ap_ramtop(void) @@ -128,7 +128,7 @@
/* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if (bsp_topmem2() > (uint64_t)1<<32) { + if (bsp_topmem2() > (uint64_t)1 << 32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if (has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB; diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index c0a69ec..5548007 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -43,7 +43,7 @@ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4
/* Get the cpu_init_detected */ diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index c4eb50c..a04ec55 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -64,7 +64,7 @@ u32 val; dev = get_node_pci(nodeid, 0); val = pci_read_config32(dev, 0x68); - val |= (1<<17)|(1<<18); + val |= (1 << 17)|(1 << 18); pci_write_config32(dev, 0x68, val); } } diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index db779fa..e716caf 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -82,7 +82,7 @@ addrsize_no_MSR: movl $1, %eax cpuid - andl $(1<<6 | 1<<17), %edx /* PAE or PSE36 */ + andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ jz addrsize_set_high movl $0x0f, %edx
@@ -208,7 +208,7 @@
/* MTRR registers are shared between HT siblings. */ movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(1<<12), %eax + movl $(1 << 12), %eax xorl %edx, %edx wrmsr
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5c88dfa..8d9a4dc 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -42,8 +42,8 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22
-#define SMRR_SUPPORTED (1<<11) -#define EMRR_SUPPORTED (1<<12) +#define SMRR_SUPPORTED (1 << 11) +#define EMRR_SUPPORTED (1 << 12)
struct smm_relocation_params { u32 smram_base; diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 1da7a4b..387fb8b 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -28,7 +28,7 @@ #include <console/console.h> #include "smi.h"
-#define SMRR_SUPPORTED (1<<11) +#define SMRR_SUPPORTED (1 << 11)
#define D_OPEN (1 << 6) #define D_CLS (1 << 5) diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 8ddc931..480f61a 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -190,7 +190,7 @@
/* Enable APIC */ msr = rdmsr(0x1107); - msr.lo |= 1<<24; + msr.lo |= 1 << 24; wrmsr(0x1107, msr);
/* Turn on cache */ diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 3a6c1a0..7d6338e 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -104,12 +104,12 @@ * This MSR is not documented by VIA docs, other than setting these * bits */ msr = rdmsr(NANO_MYSTERIOUS_MSR); - msr.lo |= ( (1<<7) | (1<<4) ); + msr.lo |= ( (1 << 7) | (1 << 4) ); /* FIXME: Do we have a 6-bit or 7-bit VRM? * set bit [5] for 7-bit, or don't set it for 6 bit VRM * This will probably require a Kconfig option * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ - msr.lo |= (1<<5); + msr.lo |= (1 << 5); wrmsr(NANO_MYSTERIOUS_MSR, msr);
/* Set the maximum frequency and voltage */ @@ -117,7 +117,7 @@
/* Enable TM3 */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= ( (1<<3) | (1<<13) ); + msr.lo |= ( (1 << 3) | (1 << 13) ); wrmsr(MSR_IA32_MISC_ENABLE, msr);
u8 stepping = ( cpuid_eax(0x1) ) &0xf; @@ -125,14 +125,14 @@ /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ - msr.hi |= (1<<0); /* C4e */ + msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ + msr.hi |= (1 << 0); /* C4e */ wrmsr(MSR_IA32_MISC_ENABLE, msr); }
/* Lock on Powersaver */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= (1<<20); + msr.lo |= (1 << 20); wrmsr(MSR_IA32_MISC_ENABLE, msr); }
-
HAOUAS Elyes (Code Review)