EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38999 )
Change subject: mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin ......................................................................
mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin
Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin. This can save 1mW power comsumption.
BUG=b:149289256 TEST=NA
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38999/1
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 85de173..d26abdb 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -184,9 +184,9 @@ /* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ /* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CTLESS_DET# */ +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), /* CTLESS_DET# */ /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ +/* SD_CLK */ PAD_NC(GPP_G6, NONE), /* AUD_PWR_EN */ /* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, PLTRST), /* SPK_DET# */
/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),
Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38999 )
Change subject: mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin ......................................................................
Patch Set 1: Code-Review+2
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38999 )
Change subject: mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38999 )
Change subject: mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin ......................................................................
mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin
Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin. This can save 1mW power comsumption.
BUG=b:149289256 TEST=NA
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Ivy Jian ivy_jian@compal.corp-partner.google.com Reviewed-by: Mathew King mathewk@chromium.org --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Ivy Jian: Looks good to me, approved Mathew King: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 85de173..d26abdb 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -184,9 +184,9 @@ /* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ /* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CTLESS_DET# */ +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), /* CTLESS_DET# */ /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ +/* SD_CLK */ PAD_NC(GPP_G6, NONE), /* AUD_PWR_EN */ /* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, PLTRST), /* SPK_DET# */
/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),
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EricR Lai (Code Review) -
Ivy Jian (Code Review)
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Mathew King (Code Review)
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Patrick Georgi (Code Review)