[S] Change in coreboot[main]: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR

[Krystian Hebel (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Michał Żygowski, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun, Tim Chu.

Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77445?usp=email )

Change subject: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR
......................................................................

Patch Set 19: Code-Review+2

(1 comment)

File src/soc/intel/alderlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/77445/comment/919c23b9_3ab8e882 :
PS15, Line 127: (256 * MiB)
> Done

https://review.coreboot.org/c/coreboot/+/77445/11..19/src/soc/intel/alderlak... was the reason for changing it to 0x... so I didn't comment on that, but for me also MiB looks better for sizes.