Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46979 )
Change subject: soc/intel/broadwell: Iron out more cosmetic differences ......................................................................
soc/intel/broadwell: Iron out more cosmetic differences
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I151595ba677ab4e1a3c5e40eb49f63b0b40a027c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/haswell.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/me.h M src/soc/intel/broadwell/pch/serialio.c M src/soc/intel/broadwell/pch/smbus.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/broadwell/report_platform.c 11 files changed, 138 insertions(+), 160 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46979/1
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index db9aced..3a9ac13 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -57,16 +57,16 @@
/* VTVC0BAR has to be set, enabled, and in 32-bit space */ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); + size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); acpi_dmar_drhd_fixup(tmp, current); }
diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c index fc56e4e..59c31aa 100644 --- a/src/soc/intel/broadwell/bootblock.c +++ b/src/soc/intel/broadwell/bootblock.c @@ -2,7 +2,6 @@
#include <arch/bootblock.h> #include <device/pci_ops.h> - #include "haswell.h"
void bootblock_early_northbridge_init(void) @@ -10,16 +9,14 @@ uint32_t reg;
/* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent + * non-explicit config accesses use MCFG. This code also assumes that + * bootblock_northbridge_init() is the first thing called in the non-asm + * boot block code. The final assumption is that no assembly code is using + * the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = 0; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 8370167..0c881c2 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -23,7 +23,7 @@
#include "haswell.h"
-#define GT_RETRY 1000 +#define GTT_RETRY 1000 enum { GT_CDCLK_DEFAULT = 0, GT_CDCLK_337, @@ -42,7 +42,7 @@ /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
/* Enable Counters */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), @@ -103,10 +103,10 @@ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
/* Set RC6 VIDs */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
/* Enable PM Interrupts */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), @@ -126,13 +126,13 @@
/* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
/* Enable power well for DP and Audio */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, - (1 << 30), (1 << 30), GT_RETRY), + (1 << 30), (1 << 30), GTT_RETRY),
REG_SCRIPT_END }; @@ -140,7 +140,7 @@ static const struct reg_script broadwell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
/* Enable push bus metric control and shift */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004), @@ -205,10 +205,10 @@ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000),
/* Set RC6 VIDs */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
/* Enable PM Interrupts */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), @@ -227,12 +227,12 @@
/* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY),
/* Enable power well for DP and Audio */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, - (1 << 30), (1 << 30), GT_RETRY), + (1 << 30), (1 << 30), GTT_RETRY),
REG_SCRIPT_END }; @@ -266,7 +266,8 @@ }
int gtt_poll(u32 reg, u32 mask, u32 value) -{ unsigned int try = GT_RETRY; +{ + unsigned int try = GTT_RETRY; u32 data;
while (try--) { diff --git a/src/soc/intel/broadwell/haswell.h b/src/soc/intel/broadwell/haswell.h index df3a7550..09de2ef 100644 --- a/src/soc/intel/broadwell/haswell.h +++ b/src/soc/intel/broadwell/haswell.h @@ -100,7 +100,7 @@ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 -#define MCH_PAIR 0x5418 +#define INTRDIRCTL 0x5418 #define GDXCBAR 0x5420
#define MCH_DDR_POWER_LIMIT_LO 0x58e0 diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 1409c20..8b1567e 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -53,7 +53,6 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 1319a02..5fec655 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -35,8 +35,7 @@ return pci_read_config32(sa_dev, BGSM) & ~1; }
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, - u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg;
@@ -49,19 +48,19 @@ return 0;
switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| + case 0: /* 256MB */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); *len = 256 * 1024 * 1024; return 1; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)); + case 1: /* 128M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27)); *len = 128 * 1024 * 1024; return 1; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)|(1 << 26)); + case 2: /* 64M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27) | (1 << 26)); *len = 64 * 1024 * 1024; return 1; } @@ -71,35 +70,31 @@
static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = pci_read_config32(dev, index);
- bar = pci_read_config32(dev, index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0;
- /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1;
return 1; }
-/* There are special BARs that actually are programmed in the MCHBAR. These - * Intel special features, but they do consume resources that need to be - * accounted for. */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, - u32 *len) +/* + * There are special BARs that actually are programmed in the MCHBAR. These Intel special + * features, but they do consume resources that need to be accounted for. + */ +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = MCHBAR32(index);
- bar = MCHBAR32(index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0;
- /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1;
return 1; @@ -108,24 +103,22 @@ struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(struct device *dev, unsigned int index, - u32 *base, u32 *size); + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; };
+#define SIZE_KB(x) ((x) * 1024) struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, 0x8000, get_bar, "MCHBAR" }, - { DMIBAR, 0x1000, get_bar, "DMIBAR" }, - { EPBAR, 0x1000, get_bar, "EPBAR" }, - { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, + { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, + { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, + { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, + { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, + { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, }; +#undef SIZE_KB
-/* - * Add all known fixed MMIO ranges that hang off the host bridge/memory - * controller device. - */ +/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -138,14 +131,13 @@
size = mc_fixed_resources[i].size; index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) + if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) continue;
resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + resource->base = base; resource->size = size; printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", @@ -154,7 +146,8 @@ } }
-/* Host Memory Map: +/* + * Host Memory Map: * * +--------------------------+ TOUUD * | | @@ -167,13 +160,15 @@ * +--------------------------+ BGSM * | TSEG | * +--------------------------+ TSEGMB + * | DPR | + * +--------------------------+ (DPR top - DPR size) * | Usage DRAM | * +--------------------------+ 0 * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. + * Some of the base registers above can be equal, making the size of the regions within 0. + * This is because the memory controller internally subtracts the base registers from each + * other to determine sizes of the regions. In other words, the memory map regions are always + * in a fixed order, no matter what sizes they have. */
struct map_entry { @@ -183,14 +178,13 @@ const char *description; };
-static void read_map_entry(struct device *dev, struct map_entry *entry, - uint64_t *result) +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; uint64_t mask;
- /* All registers are on a 1MiB granularity. */ - mask = ((1ULL<<20)-1); + /* All registers have a 1MiB granularity */ + mask = ((1ULL << 20) - 1); mask = ~mask;
value = 0; @@ -217,12 +211,9 @@ .description = desc_, \ }
-#define MAP_ENTRY_BASE_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 1, desc_) -#define MAP_ENTRY_BASE_32(reg_, desc_) \ - MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_)
enum { TOM_REG, @@ -235,21 +226,21 @@ BGSM_REG, BDSM_REG, TSEG_REG, - // Must be last. - NUM_MAP_ENTRIES + /* Must be last */ + NUM_MAP_ENTRIES, };
static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), };
static void mc_read_map_entries(struct device *dev, uint64_t *values) @@ -266,22 +257,20 @@ printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", memory_map[i].description, values[i]); } - /* One can validate the BDSM and BGSM against the GGC. */ + /* One can validate the BDSM and BGSM against the GGC */ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); }
static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { - unsigned long base_k, size_k; - unsigned long touud_k; - unsigned long index; + unsigned long base_k, size_k, touud_k, index; struct resource *resource; uint64_t mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg; struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
- /* Read in the MAP registers and report their values. */ + /* Read in the MAP registers and report their values */ mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]);
@@ -299,33 +288,29 @@
/* * These are the host memory ranges that should be added: - * - 0 -> 0xa0000: cacheable - * - 0xc0000 -> TSEG : cacheable - * - TESG -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved - * - 4GiB -> TOUUD: cacheable + * - 0 -> 0xa0000: cacheable + * - 0xc0000 -> TSEG: cacheable + * - TSEG -> BGSM: cacheable with standard MTRRs and reserved + * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved + * - 4GiB -> TOUUD: cacheable * - * The default SMRAM space is reserved so that the range doesn't - * have to be saved during S3 Resume. Once marked reserved the OS - * cannot use the memory. This is a bit of an odd place to reserve - * the region, but the CPU devices don't have dev_ops->read_resources() - * called on them. + * The default SMRAM space is reserved so that the range doesn't have to be saved + * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a + * bit of an odd place to reserve the region, but the CPU devices don't have + * dev_ops->read_resources() called on them. * - * The range 0xa0000 -> 0xc0000 does not have any resources - * associated with it to handle legacy VGA memory. If this range - * is not omitted the mtrr code will setup the area as cacheable - * causing VGA access to not work. + * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to + * handle legacy VGA memory. If this range is not omitted the mtrr code will setup + * the area as cacheable, causing VGA access to not work. * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. + * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation + * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing + * MTRRs covering this region. * - * It should be noted that cacheable entry types need to be added in - * order. The reason is that the current MTRR code assumes this and - * falls over itself if it isn't. + * It should be noted that cacheable entry types need to be added in order. The reason + * is that the current MTRR code assumes this and falls over itself if it isn't. * - * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. + * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0. */ index = *resource_cnt;
@@ -365,12 +350,11 @@
/* Reserve everything between A segment and 1MB: * - * 0xa0000 - 0xbffff: legacy VGA + * 0xa0000 - 0xbffff: Legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); @@ -378,43 +362,40 @@ *resource_cnt = index; }
-static void systemagent_read_resources(struct device *dev) +static void mc_read_resources(struct device *dev) { int index = 0; - const bool vtd_capable = - !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
- /* Read standard PCI resources. */ + /* Read standard PCI resources */ pci_dev_read_resources(dev);
- /* Add all fixed MMIO resources. */ + /* Add all fixed MMIO resources */ mc_add_fixed_mmio_resources(dev);
- /* Add VT-d MMIO resources if capable */ + /* Add VT-d MMIO resources, if capable */ if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, - GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, - VTVC0_BASE_SIZE / KiB); + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); }
- /* Calculate and add DRAM resources. */ + /* Calculate and add DRAM resources */ mc_add_dram_resources(dev, &index); }
-static void systemagent_init(struct device *dev) +static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair;
/* Enable Power Aware Interrupt Routing */ - pair = MCHBAR8(MCH_PAIR); + pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ pair |= 0x4; /* Fixed Priority */ - MCHBAR8(MCH_PAIR) = pair; + MCHBAR8(INTRDIRCTL) = pair;
/* - * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management + * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management. */ bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); bios_reset_cpl |= 3; @@ -426,12 +407,12 @@ set_power_limits(28); }
-static struct device_operations systemagent_ops = { - .read_resources = systemagent_read_resources, +static struct device_operations mc_ops = { + .read_resources = mc_read_resources, .acpi_fill_ssdt = generate_cpu_entries, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = systemagent_init, + .init = northbridge_init, .ops_pci = &pci_dev_ops_pci, };
@@ -444,7 +425,7 @@ };
static const struct pci_driver systemagent_driver __pci_driver = { - .ops = &systemagent_ops, + .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = systemagent_ids }; @@ -461,10 +442,10 @@ static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = &mp_cpu_bus_init, + .init = mp_cpu_bus_init, };
-static void broadwell_enable(struct device *dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -476,6 +457,6 @@
struct chip_operations soc_intel_broadwell_ops = { CHIP_NAME("Intel Broadwell") - .enable_dev = &broadwell_enable, - .init = &broadwell_init_pre_device, + .enable_dev = enable_dev, + .init = broadwell_init_pre_device, }; diff --git a/src/soc/intel/broadwell/pch/me.h b/src/soc/intel/broadwell/pch/me.h index 5282441..df71fca 100644 --- a/src/soc/intel/broadwell/pch/me.h +++ b/src/soc/intel/broadwell/pch/me.h @@ -436,7 +436,7 @@ u16 lock_state : 1; u16 authenticate_module : 1; u16 s3authentication : 1; - u16 flash_wear_out : 1; + u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 reserved : 11; } __packed tdt_state_flag; diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/soc/intel/broadwell/pch/serialio.c index 97372e3..0c079be 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/soc/intel/broadwell/pch/serialio.c @@ -143,7 +143,7 @@ { if (acpi_mode) { /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */ - RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5)); + RCBA32_OR(ACPIIRQEN, (1 << 13) | (1 << 7) | (1 << 6) | (1 << 5)); }
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */ diff --git a/src/soc/intel/broadwell/pch/smbus.c b/src/soc/intel/broadwell/pch/smbus.c index 76562ce..da0ca87 100644 --- a/src/soc/intel/broadwell/pch/smbus.c +++ b/src/soc/intel/broadwell/pch/smbus.c @@ -19,7 +19,7 @@ /* Enable clock gating */ /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */ reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); + reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)); pci_write_config32(dev, 0x80, reg16);
/* Set Receive Slave Address */ diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index 270b4d2..6304194 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -377,7 +377,7 @@ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - disable_pm1_control(-1UL); + disable_pm1_control(-1); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); } } @@ -430,7 +430,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); + pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index ad5a109..b02b234 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -87,7 +87,7 @@ strcpy(cpu_string, "Platform info not available"); } else { u32 *p = (u32 *)cpu_string; - for (i = 2; i <= 4 ; i++) { + for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; *p++ = cpuidr.ebx;
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46979
to look at the new patch set (#4).
Change subject: soc/intel/broadwell: Iron out more cosmetic differences ......................................................................
soc/intel/broadwell: Iron out more cosmetic differences
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I151595ba677ab4e1a3c5e40eb49f63b0b40a027c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/haswell.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/me.h M src/soc/intel/broadwell/pch/serialio.c M src/soc/intel/broadwell/pch/smbus.c M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/broadwell/pch/usb_ehci.c M src/soc/intel/broadwell/pch/usb_xhci.c M src/soc/intel/broadwell/report_platform.c 14 files changed, 143 insertions(+), 167 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46979/4
-
Angel Pons (Code Review)