Hello Hung-Te Lin, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, EricR Lai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48980
to review the following change.
Change subject: Revert "mb/google/brya: Initiate peripheral buses" ......................................................................
Revert "mb/google/brya: Initiate peripheral buses"
This reverts commit 5bb5c43b936f0bb01e08a71df1865343d7be9b88.
Reason for revert: Build bot fails.
Change-Id: I8f022514351b37be135d10ef8486e4aa5fd6361b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48980/1
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 96e0a9d..479a7ee 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,113 +3,6 @@ device lapic 0 on end end
- register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2_C0 - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB2_C1 - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # USB2_C2 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - - # Enable WLAN PCIE 5 using clk 2 - register "pch_pcie_rp[PCH_RP(5)]" = "{ - .clk_src = 2, - .clk_req = 2, - .flags = PCIE_RP_ENABLED, - }" - - # Enable WWAN PCIE 6 using clk 5 - register "pch_pcie_rp[PCH_RP(6)]" = "{ - .clk_src = 5, - .clk_req = 5, - .flags = PCIE_RP_ENABLED, - }" - - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_ENABLED | PCIE_RP_HOTPLUG_ENABLED | PCIE_RP_LTR_ENABLED, - }" - - # Enable NVMe PCIE 9 using clk 1 - register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, - .flags = PCIE_RP_ENABLED | PCIE_RP_LTR_ENABLED, - }" - - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - }" - - register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 1, - }" - - register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 1, - }" - - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoPci, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI1 | Fingerprint MCU | - #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | SAR0 | - #| I2C3 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| I2C4 | CAM | - #| I2C5 | Trackpad | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - device domain 0 on device ref igpu on end device ref dtt on end @@ -137,6 +30,7 @@ device ref pcie_rp8 on end #PCIE8 SD card device ref pcie_rp9 on end #PCIE9-12 SSD device ref uart0 on end + device ref gspi0 on end device ref gspi1 on end device ref pch_espi on chip ec/google/chromeec
Hello Hung-Te Lin, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48980
to look at the new patch set (#2).
Change subject: Revert "mb/google/brya: Initiate peripheral buses" ......................................................................
Revert "mb/google/brya: Initiate peripheral buses"
This reverts commit 5bb5c43b936f0bb01e08a71df1865343d7be9b88.
Reason for revert: Build bot fails.
Change-Id: I8f022514351b37be135d10ef8486e4aa5fd6361b Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48980/2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48980 )
Change subject: Revert "mb/google/brya: Initiate peripheral buses" ......................................................................
Patch Set 2: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48980 )
Change subject: Revert "mb/google/brya: Initiate peripheral buses" ......................................................................
Patch Set 2:
It looks like this was submitted out-of-order without its prerequisites. Please just push the commit as a new change again.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48980 )
Change subject: Revert "mb/google/brya: Initiate peripheral buses" ......................................................................
Patch Set 2: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48980 )
Change subject: Revert "mb/google/brya: Initiate peripheral buses" ......................................................................
Patch Set 2:
submitting early as this breaks other builds
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48980 )
Change subject: Revert "mb/google/brya: Initiate peripheral buses" ......................................................................
Revert "mb/google/brya: Initiate peripheral buses"
This reverts commit 5bb5c43b936f0bb01e08a71df1865343d7be9b88.
Reason for revert: Build bot fails.
Change-Id: I8f022514351b37be135d10ef8486e4aa5fd6361b Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/48980 Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 107 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 96e0a9d..479a7ee 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,113 +3,6 @@ device lapic 0 on end end
- register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2_C0 - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB2_C1 - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # USB2_C2 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - - # Enable WLAN PCIE 5 using clk 2 - register "pch_pcie_rp[PCH_RP(5)]" = "{ - .clk_src = 2, - .clk_req = 2, - .flags = PCIE_RP_ENABLED, - }" - - # Enable WWAN PCIE 6 using clk 5 - register "pch_pcie_rp[PCH_RP(6)]" = "{ - .clk_src = 5, - .clk_req = 5, - .flags = PCIE_RP_ENABLED, - }" - - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_ENABLED | PCIE_RP_HOTPLUG_ENABLED | PCIE_RP_LTR_ENABLED, - }" - - # Enable NVMe PCIE 9 using clk 1 - register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, - .flags = PCIE_RP_ENABLED | PCIE_RP_LTR_ENABLED, - }" - - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - }" - - register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 1, - }" - - register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 1, - }" - - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoPci, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI1 | Fingerprint MCU | - #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | SAR0 | - #| I2C3 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| I2C4 | CAM | - #| I2C5 | Trackpad | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - device domain 0 on device ref igpu on end device ref dtt on end @@ -137,6 +30,7 @@ device ref pcie_rp8 on end #PCIE8 SD card device ref pcie_rp9 on end #PCIE9-12 SSD device ref uart0 on end + device ref gspi0 on end device ref gspi1 on end device ref pch_espi on chip ec/google/chromeec
-
Felix Singer (Code Review) -
Nico Huber (Code Review)
-
Tim Wawrzynczak (Code Review)